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Maximum throughput on GPMC?

B.J. Buchalter
Intellectual 875 points

I have read through the datasheet and the TRM for the TMS320C6A816x and unfortunately they appear to be in conflict for the maximum data throughput on the GPMC. What is the maximum possible burst data throughput via the GPMC? Does it depend on whether the target device is Asynchronous or Synchronous? Ideally, I would prefer to use a Synchronous port as my target will be an FPGA. The TRM appears to imply that with proper register configuration I could get a burst transfer rate of 125MHz x 2bytes per transfer. The data sheet seems to imply that the max rate would b 62.5 MHz x 2 bytes per transfer. Which is correct? 

Is there any sample code or discussion about how to configure a bank on the GPMC for maximum possible transfer rate?

 

TIA,

B.J.

  • 0
    Intellectual 875 points
    Steve, Understood; both source and destination would be an FPGA, so that is possible; but I still need documentation about the I/O peripherals in the TMS320C6A8168 in order to design the cores and write the drivers. As far as I know, that is not publicly documented yet. How do I go about getting my hands on the docs? Best regards, B.J.
  • 0
    Intellectual 875 points
    Hi Marc,

    The part that I would be interfacing to would be an FPGA; I don't see why running a sync interface with a single transfer per 8ns clock would be a problem to accomplish if the the GPMC can actually be programmed to do so. The idea is that I will have a large amount of data streaming into the C6A816x via PCIe and GigE, and I will have a large amount of data streaming into the FPGA; the data from the FPGA needs to get into the C6A816x for processing via the DSP, and then the results need to be streamed back to the FPGA.

    The data is not video data; so while I might be able to adapt the DVO and VIDCAP interfaces for this purpose, it is not a great fit, *especially* since there is no documentation available for those peripherals available.

    GPMC being able to do 125Mhz * 16 bit transfers would do the job. It might be possible to use one of the GMAC ports for this purpose as well, although there is obviously some packet overhead there, and I would need to figure out how to grab control of the GMAC from Linux. Ideally, being able to schedule DMA over the GPMC to my FPGA would be the best conceptually, as long as I can get enough throughput. 125Mhz * 16 bit should be enough. 62.5Mhz * 16 bit might be enough. Lower than that may not provide enough bandwidth for all possible applications that we need to support.

    Best regards,

    B.J.