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TDA4VM: TDA4VM

Part Number: TDA4VM

Hello, i have any question

We are making PCB artwork data for TDA4VM System, We have to choice PCB's material

I know that TI  suggests I-SPEED material for highest rates but we want to choice FR-4 material

1. please check below TI recommended PCB Spec VS our PCB spec                       

  • Layer           : 16 Layer – 14Layer
  • Thickness    :  2.1T –1.6T
  • Material       : I-Speed – FR-4 (Middle TG)
  • Back-drill     : Yes – No
  • Via protection : H.P.L (Hole Plugging Land) –P (Hole Plugging) ; No, Pad in Via

2. do you have any Design guide for FR-4 material ?

thanks.

  • There are two PCB design application notes for TDA4VM.  Both are NOT material specific.

    Jacinto7 LPDDR4 Design Guidelines:  https://www.ti.com/lit/pdf/spracn9

    Jacinto7 High Speed Design Guidelines:  https://www.ti.com/lit/pdf/spracp

    Depending upon the number of interfaces/signals the design uses, yes the layer count could be reduced from our example of 16L.

    The PCB material can also be changed from our example (I-Speed).  FR4 will have more loss, and those affects will need to be accounted for in the design.  Especially for the highest rate interfaces (LPDDR4, PCIe, etc)   Its possible you may sacrifice performance with a lower cost PCB.

    Back-drill requirements are again dependent on the specific design.  With carefully layer/route planning, via stubs can be minimized.  Again - its the very highest speed interfaces that are most impacted (LPDDR4, PCIe, etc.)