AM572X: GPIO interrupt and system interconnect questions

Anjana,

I created a separate thread with your last query from previous E2E thread as it is not related the GPIO LLD software. I am assigning it to the hardware team who will get back to you on your questions regarding the interconnect and the TRM.

Regards,
Rahul

Hi,

I am waiting for reply....................

Please do the needful.........

Anjana

It is almost 4 days are gone and i have not yet received any reply.

Please look into it....... 

Anjana,
sorry for the delay....I am checking with apps what is going on...

Thanks a lot for your reply...

in #2 my question is

What is two identical submodules?

What is biprocessor environment?

in #3 i will go through interconnect chapter in TRM.

Waiting for #1 answer....

Thanks,

Anjana Pathak

Hi Anjana,

1. Can you share why you are concerned about the pulse width or why this is important for your application? Note that the GPIO IP has a debouncing feature, if that is part of your concern.

2. Within the GPIO IP, there are two submodules that process interrupt requests. The best pictorial view I found is Figure 27-8. This doesn’t distinctly show the two submodules, but you can see that 2 synchronous interrupt requests can be generated (by the submodules, not shown). Biprocessor environment means an environment or application that uses multiple processors within the AM57x (i.e. ARM & DSP) and requires both processors to be interrupted by the GPIO.

Regards,
Melissa

Hi Melissa,

Thanks a lot...........

My requirement is to sense pulse of 1 microsecond to 50 nanosecond on-time width at input.

  I am using User1, User2 Push button of LCD module which are connected to GPIO2_23 and GPIO_25 of AM572x.

I configure these GPIO pins as input, interrupt on both the edges.

So for this I want to know weather these GPIOs will give proper result with the required pulse width i.e. 1 micro to 50 nano sec or I need to do some configuration changes for GPIO module?

  Thanks,

Anjana

Please reply...........

Anjana

I don,t know why there is no reply for my query.

Is that my question is not clear?

Anjana,
Thanks for waiting....our apps team will reply soon.

Hi Melissa,

Yes I am calculating the pulse width based on rising and falling edge interrupts.

I donot want to ignore any pulse width, in fact i want all pulse widths to be read.

I want to know what is the minimum pulse width i can measure? Is it possible to measure 50ns pulse width?

I am using TI RTOS. processor_sdk_rtos_am57xx_3_02_00_05.

Thanks,

Anjana Pathak 

Anjana,

From OS perspective the interrupt latency is 739 cycles on the ARM so you may not be able to meet 50ns pulse width requirement from the ARM using TI RTOS.

Check the TI RTOS interrupt latency in the following location.
bios_6_46_04_53/packages/ti/sysbios/benchmarks/doc-files/GCC_A15F_ti_platforms_evmDRA7XX_time.html

Regards,
Rahul

Hi Anjana,

Another alternative is to use the PRU-ICSS to monitor and measure the push button pulse width.

The PRU-ICSS has dedicated fast I/Os, and the following lab describes how the PRU can be used to detect a push button switch:

processors.wiki.ti.com/.../PRU_Training:_Hands-on_Labs

You can then use the PRU_CYCLE register to count the number of cycles between the rising and falling edges. For example, enable PRU_CONTROL[COUNTER_ENABLE] immediately after you detect the first edge, then wait for the second edge. Upon detecting the second edge, immediately disable the counter and then read the PRU_CYCLE register to determine the pulse width.

This method would be able detect pulse widths as low as 20 ns.

Regards,

Melissa

Thanks a lot Rahul............

I will go through the given doc file.

Anjana Pathak 

Thanks Melissa..
I will go through the training..
and will also try with PRU_CYCLE.

Anjana Pathak

Anjana,

You may also be interested in the GPIO LLD benchmarks that have been discussed here. This will provide you an additional data point on top of the RTOS Interrupt latency benchmarks.
e2e.ti.com/.../2109849

I agree with Melissa recommendation to look at a PRU/ICSS based implementation may meet your requirements.

Regards,
Rahul

Hi Rahul,

As i am using TiRTOs the interrupt latency is 739 cycles on the ARM Cortex A15 means in terms of period it is 0.739 microsecond ?

thanks,

Anjana Pathak

Yes, at OPP_NOM (1GHz), 739 cycles translates to 0.739 microseconds.

Regards,

Rahul

hi,

In the link processors.wiki.ti.com/.../PRU_Training:_Hands-on_Labs labs can be used for GP EVmAm572x?

Anjana Pathak

Hi Anjana,

The labs were written for AM335x but can be easily modified for AM57x. For example, the primary changes for Lab 2 (Read Push Button Switch) would be as follows.

- Step 2b. Select “AM5728” instead of “BeagleBone_Black”
- Step 3. Replace “AM335x_PRU.cmd” with “AM57xx_PRU.cmd” (available in the pru/include folder within CCS)
- Step 5e. Update this for whatever GPI you want to use on the GP AM572x EVM. Pinmuxing in the gel file will also need to get updated.
- Step 8c. Update this for whatever GPO you want to use on the GP AM572x EVM. Pinmuxing in the gel file will also need to get updated.

There's also an AM335x to AM57x PRU migration guide that can be referenced when modifying the labs for AM57x.
processors.wiki.ti.com/.../PRU-ICSS_Migration_Guide:_AM335x_to_AM57x

Regards,
Melissa

Thanks Melissa........
Sorry for late reply
I will try the above lab explained by you.

Regards,
Anjana Pathak

Hi Melissa,
I tried the lab 3 PRU_HDQ_TempSensor0 from PRU software package.
The code get compiled but when i want to load the program through XDS200 it is giving following error
"Cortex_M4_IPU1_C0: Error connecting to the target: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.222.0) " while configuring debugger. how to remove this error?

Thanks,
Anjana Pathak