TMS320C6455DSK: using EMIF in synchronous mode

Francesco Annese,

Where did you read "the asynchronous mode is the only one that could work on the board"?

It looks like the DSK brings all of the EMIFA signals to the daughtercard connectors, so you can connect anything you want and use the signals any way you want. For any mode that you want to use, verify on the board schematic that all of the signals you need to use are made available on the daughtercard connector.

Regards,
RandyP

If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.

RandyP,

I found this thread in the Forum archives: http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/t/11642.aspx

TI Employee tscheck wrote: "Remember, the daughter card expansion slot only provides access to the DSP Asynchronous EMIF signals.  You can't run a synchronous interface on this connector.  Be sure to look at CEnCFG registers for SSEL =0." Moreover, the Technical Reference documentation states that  "The memory connector provides access to the DSP’s asynchronous EMIF signals to interface with memories and memory mapped devices" (page 2-9). I thought that was why I wasn't able to use the EMIF interface in synchronous mode.

Anyway, I'll try again with synchronous mode at the beginning of next week, in case it didn't work because of  a mistake by me.

Actually I only need the data lines at the moment, so if it could be possible to use the interface in synchronous mode regardless of what other signals are available on the connector, that could be a good starting point to see if I can achieve the transfer speed I need.

Many thanks,

Francesco Annese

Francesco Annese,

I have noticed your post yesterday and I have observed the same problem with you.

I need a sampling speed at least of 30MHz to access the ADC/DAC connected through the EMIF. The data transfer operation is triggered by the Timer interrupt. However, when I set the Timer speed above 16 MHz, I observed by the oscilloscope that  the data output (switch between 0 and 1) at  ED0 pin of the EMIF connector (J4 on DSK 6416) remains 16MHz. The data output switch speed can not catch the Timer clock operation frequenc when the Timer operatioin frequency is higher than 16MHz.. I have set the Write/Read Setup=Strobe=1, Hold=0 ECLKOUT for maximum speed.  I also tried to make the EMIF work at synchronous mode by setting the CEx control register (MTYPE = 0100: 32bit SBSRAM). But the result doesnot change. Your findings about the EMIF connector on DSK board  doesnot provide access to synchronus mode signal transfer noticed me..

Currently, I am also seeking the way to make the EMIF work at synchronous mode to achieve the transfer speed I need. And I will appreciate greatly if you could share your new findings in next week.

Thanks,

Sung Kim

Francesco Annese,

tscheck knows what he is talking about. Thank you for referencing his post. I did not look far enough on the schematic to confirm the points that he made. The signal ASADS*/ASRE* is not brought to the daughtercard connecter, and it appears AR/W* is also not brought out on later revisions of the board.

Vito Francesco Annese said:

Actually I only need the data lines at the moment, so if it could be possible to use the interface in synchronous mode regardless of what other signals are available on the connector, that could be a good starting point to see if I can achieve the transfer speed I need.

I do not see any reason why you cannot do this, but you will have to make sure that you do not need the qualification of the SRE signal. Of course, I did not know the limitations of the daughtercard connector, so please trust your tests and not my advice on this point.

Regards,
RandyP

EDIT: Do not mind my question about the CPLD source code location, I found it in a .zip package on the Spectrum Digital Support page. Its content should have been identical to that in the cd that comes with the dsk box, but those source files are not in the cd.

Hi RandyP,

I tried again to use EMIF in synchronous mode with different settings for its parameters, but it didn't work.

I had a better look at the schematics: I already knew that the CPLD outputs a couple of signals towards the data buffer between the J4 connector and the DSP. Those are  DC_EMIFA_OE# and DC_EMIFA_DIR; the former is used to enable the buffer, the latter sets the direction. What I found is that the R/W, AWE/SWE and AOE/SOE signals go from  the DSP to the CPLD and this made me think DC_EMIFA_OE# and DC_EMIFA_DIR are produced as a function of some of those other input signals to the CPLD. It could be the reason why the buffer doesn't let the data signal through when EMIF is in synchronous mode (since R/W is only used in asynchronous mode and SRE is not connected).

I looked for the source code used to program the CPLD in order to understand how DC_EMIFA_OE# and DC_EMIFA_DIR are determined, but could not find it. In the Technical Reference I read that  "The CPLD source files are written in the industry standard VHDL (Hardware Design Language) and included with the DSK", so are they available in some folder?

I wonder if I could set the CPLD to enable the buffer no matter what; it should be enough to use the EMIF in synchronous mode.

Any clue as to find the source code implemented in the CPLD?

Regards,

Francesco Annese

So, back with some news: I had a look at the CPLD source code and found these lines:

DC_DBUF_DIR <= not DSP_ARNW; -- low for write, high for read
 
DC_DBUF_OEn <= '0' when DC_DETn    = '0' 
                     and ( DcCs0 = '0' or  DcCs1 = '0' )
                             and ( DSP_OEn  = '0' or  DSP_WEn = '0'  )                                            
                             else '1';

In order to let the signal through, the data buffers between the J4 connector and the DSP need both DC_EMIFA_DIR (corresponding to DC_DBUF_DIR) and DC_EMIF_OE# (corresponding to DC_DBUF_OEn). While the latter is provided both in asynchronous and synchronous mode, the former is provided only in asynchronous mode since it is a function of the asynchronous R/W signal.  So I changed the code in the CPLD in order to provide that signal anyway:

DC_DBUF_DIR <= '0';

This way I could use the EMIF interface in synchronous mode, but the buffer direction is now set as "input only". I was able to correctly acquire the data signal using a clock up to 27 MHz, but errors occurred for 54 and 40 MHz clocks. I think the problem could be related to the GPIO pin: maybe the rate of the clock signal is too high and not all the transitions on the pin can be taken into account to trigger EDMA transfers.

I'll try to trigger the first EDMA transfer with an external event and then chain all the others to see if it is a GPIO limit.

Regards,

Francesco Annese

Francesco Annese,

I am really glad to hear that you succeeded in making the EMIF work under synchronous mode..

By the way, could you please show where is the source file of the CPLD and the name of source code?

Thanks a lot !

Regards,

Sung Kim

Sung Kim,

I found the whole CPLD code project (including the .vhd file I modified) in a .zip package available on the Spectrum Digital support page; the package is specific to the board I'm using. It could also be placed in the folder of the board, together with bsl and csl folders; look for a folder named "hwdesignsource".

Regards,

Francesco Annese

Francesco Annese,

I will check for that

Thank you very much

Regards,

Sung Kim

It seems that my speed problem is not related to the rate at which the GPIO pin toggles: even if I chained all transfers following the first one, the data acquired weren't correct and didn't look like oversampled data at all.

Since the transfer is accomplished by the EDMA module, I'm not worried about any other task the CPU could possibly be involved in; or should I? Could there be unexpected contention of the EMIF bus?

I'm really looking for suggestions, everything I tried is still not enough to solve my problem.

Here are the settings for both EDMA and EMIF, maybe there's something wrong with them:

//EDMA

edmaParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS,
                                             CSL_EDMA3_TCCH_DIS,
                                             CSL_EDMA3_ITCINT_DIS,
                                             CSL_EDMA3_TCINT_EN,
                                             61,
                                             CSL_EDMA3_TCC_EARLY,
                                             CSL_EDMA3_FIFOWIDTH_NONE,
                                             CSL_EDMA3_STATIC_DIS,
                                             CSL_EDMA3_SYNC_A,
                                             CSL_EDMA3_ADDRMODE_INCR,
                                             CSL_EDMA3_ADDRMODE_INCR);
  edmaParamSetup.srcAddr = 0xC0000000;
  edmaParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(4, 1000);
  edmaParamSetup.dstAddr = (Uint32)mem;
  edmaParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0, 8);
  edmaParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL, 0);
  edmaParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0);
  edmaParamSetup.cCnt = 1;

//EMIF

emifaSync.sbsize = 0x02;
emifaSync.r_ltncy = 0x01;
emifaSync.readEn = 0x00;
emifaSync.readByteEn = 0x00;
emifaSync.chipEnExt = 0x00;

What I'm trying to do is reading a number of  words from the EMIF interface, one word per clocked GPIO event (it acts as a "data ready" signal), and I need to to that with a 40 MHZ clock on the GPIO.

Hope someone can give me a clue, any clue; even an authoritative "This can't be done" would be enough, at least I'd stop looking for a non-existing solution.

Francesco Annese,

You have many variables here:

• EVM or your own board
• No additional logic or custom daughtercard
• DSP maximum capability or achievable within your constraints here
• Delays from GPIO pin to EDMA3 to EMIFA to device
• Nature of the device being read
• Custom changes to the CPLD and delays through the CPLD
• ECLKIN and ECLKOUT rate

There will be a delay from the edge of your GPIO signal rising until you see an EMIF signal starting to do the read. What is this amount of time from your async tests and now your sync tests?

What is the delay from the beginning of the EMIF signal changes (CEn low, if that is first) until the read is completed (CEn high or ARE high, for example)?

What you are trying to do is not trivial, but it is not possible for us to tell you it is possible or impossible. These measurements are part of what you will require to be able to do you system analysis to determine if it will work for your system.

You might need to change the way you capture data, such as using a daughtercard that will buffer data and build a wider word to allow multiple words to be read per cycle or in a burst.

Regards,
RandyP