How do I understand DM8168 DDR schematic problem?

Hello,

For the DDR data pins, data swizzling (i.e. DM8168 D0 pin goes to memory D2 pin) is a common practice.  It is okay to rearrange the data bits within a byte.

Regards,
Marc

Thank you for your replay,but I still do not understand,please tell me,what information I can refer to?

In addition,I want to change it to 16-bit DDR chips,may you give me a  reference to it?

Thank you.

Within a particular data byte it is OK to send a particular data bit to any of the DDR data bits since as long as the DSP reads back from the same bit it writes to then it will not even know that there has been a switching of the data bits.

You can only do this 'swizzling' within a data bytes since there are other signals which are passed per byte, such as DQS, so the timing relationship between each DQS signal and its associated data byte must be maintained.

Note, you cannot do the same 'trick' with the address bits since specific 'commands' are sent across the address lines during DDR configuration, but there are no commands sent across the data lines so as long as the DSP reads back exactly what it writes, then the actual ordering does not matter.

BR,

Steve

Well,Thank you,now I seem to understand.The following picture or the PDF file of in attrachment is my design,please help me see it,is there any problems?Thank you very much!

7563.SCHEMATIC1 _ SH22 - EMIF DDR0 B.pdf