We need to interface C6472 DSP with Xilinx FPGA on a custom board. We have two links between DSP and FPGA: sRIO or EMAC.
Using the sRIO requires an expensive core. Here the price is going to be a barrier so we are looking into using the EMAC of the DSP as data link. We wouldn't be running any high level protocol such as IP/UDP/TCP.
I'm hoping to achieve 100MB/sec bidirectionnally per EMAC (1Gbit / full duplex). Does that sound feasible?
We would need to develop a low level driver for EMAC. The CSL doesn't seem to have any example about the EMAC. Everything seems to be in the NDK which does not have low level examples.
I found this AN on the web: "SW Operation of Gigabit Ethernet Media Access Controller on TMS320C645x DSP" which provides low level examples for the C6455. Is there such document / source code for the C6472?