C6655 DDR3 Memory Controller RD_LOCAL_ODT setting

John Curnow

In section 4.23 of SPRUGV8E, DDR3 Memory Controller Registers, the DDR_PHY_CTRL_1 register is described. The three LOCAL_ODT fields are each two bits, but there is no explanation of what the four possible settings do for each field. In particular, the RD_LOCAL_ODT field (bits 9-8) defaults to 0x01, which I believe means 'Full Thevenin Termination'. I assume that setting this field to 0x00 disables the termination, but what termination do the 0x10 and 0x11 settings provide?

Thanks, John.

over 10 years ago

0 Raja over 10 years ago

TI__Guru* 81335 points

Hi,

Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com).

We will get back to you on your query shortly. Thank you for your patience.

0 Senthilkumar Srinivasan over 10 years ago

TI__Mastermind 43660 points

Hello John,

I believe the below threads would be helpful to clarify your queries. Let me know if you need further inputs.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/205246/727991#727991

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/220817

Regards,

Senthil

0 John Curnow over 10 years ago in reply to Senthilkumar Srinivasan

Prodigy 30 points

Hi Senthil,
I did see these two threads previously. Neither is specific to the C6655. The first one is more concerned with IBIS models and the second one doesn't answer the question either.

It seems the documentation is lacking for the options of these three local terminations. I can understand setting IDLE_LOCAL_ODT and WR_LOCAL_ODT to 0 to disable them. That makes sense, even if the values for the other options are not given. However, the RD_LOCAL_ODT field has four possible settings. The default value of 1 seems to be recommended, but what termination resistance does it provide in the C6655? What terminations are set if RD_LOCAL_ODT is 10 or 11?

Thanks,
John

0 Tom Johnson 16214 over 10 years ago in reply to Senthilkumar Srinivasan

TI__Mastermind 46460 points

John,

The values listed in the DDR3 UG SPRUGV8 are the only values supported. The other settings are reserved.

The links provided by Senthil provide related guidance to these settings and their use in IBIS simulations.

Tom

0 John Curnow over 10 years ago in reply to Tom Johnson 16214

Prodigy 30 points

Tom,
Thank you for the clarification. SPRUGV8 should mention that the default settings are the only ones supported and the other settings are reserved. Another way to document them would be to not mention them at all. Bits 13-8 could be Reserved with a default value of 000001.

Thanks,
John

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C6655 DDR3 Memory Controller RD_LOCAL_ODT setting