AM335x EDMA Interrupt documentation (Transfer Conpletion Interrupt Shadow Region?)

Hi,

I will forward this to the factory team.

Hi Frank,
After investigating your question, there seems to be several inconsistencies in the TRM concerning the features available in the EDMA. I will try to summarize them here, and get them fixed in the next revision of the TRM. All references below refer to the latest TRM, rev L, on the web.

1. The following describes the EDMA Channel Controller (referred to as EDMA3CC or TPCC in the TRM)

AM335x only supports 4 shadow regions (not 8):
Shadow region 0: 1 transfer completion interrupt going to MPU Subsystem only (tpcc_int_pend_po0). This is Interrupt 12 in Table 6-1 ARM Cortex-A8 Interrupts.
Shadow region 1: 1 transfer completion interrupt going to the PRU-ICSS Subsystem only (tpcc_int_pend_po1) . This interrupt is Interrupt 63 shown in Table 4-21
Shadow regions 2-3: no interrupts are associated with these regions.

Regions 4-7 do not exist on AM335x

The chapter also describes a global completion interrupt. This interrupt is not implemented on AM335x

The Channel Controller (EDMA3CC) also has 1 error interrupt (Int14 tpcc_errint_pend_po) and 1 Memory Protection interrupt (Int13 tpcc_mpint_pend_po)

2. The following describes the EDMA Transfer Controller (referred to as EDMA3TC or TPTC in the TRM)

There are 3 Transfer Controllers. Transfer requests are submitted to each TC by the Channel Controller. Each Transfer Controller has 1 error interrupt:
TPTC0: tptc_erint_pend_po (TCERRINT0) goes to MPU Subsystem (Int 112 in Table 6-1) and PRU-ICSS (Int 61 in Table 4-21)
TPTC1: tptc_erint_pend_po (TCERRINT1) goes to MPU Subsystem (Int ) only
TPTC1: tptc_erint_pend_po (TCERRINT2) goes to MPU Subsystem (Int ) only

I’ll get this cleaned up in the TRM

Regards,
James

Hi James,

thanks for your answer, it makes things much more clear.

JJD said:

The chapter also describes a global completion interrupt. This interrupt is not implemented on AM335x

Does this mean that I always have to use the shadow registers EDMA3CC_S_IER(0) etc. at 0x49002000 etc. or will the global registers EDMA3CC_IER etc. at 0x49001000 etc. work too?

JJD said:

TPTC1: tptc_erint_pend_po (TCERRINT1) goes to MPU Subsystem (Int ) only
TPTC1: tptc_erint_pend_po (TCERRINT2) goes to MPU Subsystem (Int ) only

I think there is a typo, and TPTC1 and TPTC2 go to MPU Interrupts 113, 114 as listed in table 6-1, right or not?

By the way, there are "several inconsistencies" in the SDK 1.0.0.6 EDMA software too. C:\ti\am335x_sysbios_ind_sdk_1.1.0.6\sdk\starterware\include\edma.h seems to be written for other SOCs with other implementations of TPCC / TPTC EDMA, not for _this_ AM335x (see below). C:\ti\am335x_sysbios_ind_sdk_1.1.0.6\sdk\starterware\examples\evmAM335x\edma\edmaTest.c does not use these interrupt defs, so may be it works...

Regards,

Frank

Parts of C:\ti\am335x_sysbios_ind_sdk_1.1.0.6\sdk\starterware\include\edma.h with values that do not match AM335x (no claim to be complete):

//***********************************************************************
//  Values that can be used by the application for configuration via APIs
//***********************************************************************/

/** Maximum number of EDMA Shadow regions available */
#define EDMA3_MAX_REGIONS                     (2u)

/** Number of PaRAM Sets available */
#define EDMA3_NUM_PARAMSET                    (128u)

/** Number of Event Queues available */
#define EDMA3_0_NUM_EVTQUE                    (2u)

/** Number of Transfer Controllers available */
#define EDMA3_0_NUM_TC                        (2u)

/** Interrupt no. for Transfer Completion */
#define EDMA3_0_CC_XFER_COMPLETION_INT        (11u)

/** Interrupt no. for CC Error */
#define EDMA3_0_CC0_ERRINT                    (12u)

/** Interrupt no. for TCs Error */
#define EDMA3_0_TC0_ERRINT                    (13u)
#define EDMA3_0_TC1_ERRINT                    (32u)

#define EDMA3CC_DMA_CHANNELS                  (32u)

...

#if defined(am335x) || defined(am335x_13x13) || defined(am335x_15x15) || \
    defined(c6a811x) || defined(am386x) || defined(c6741x)
#define SOC_EDMA3_NUM_DMACH                 64
#define SOC_EDMA3_NUM_QDMACH                8
#define SOC_EDMA3_NUM_PARAMSETS             256
#define SOC_EDMA3_NUM_EVQUE                 4
#define SOC_EDMA3_CHMAPEXIST                0
#define SOC_EDMA3_NUM_REGIONS               8
#define SOC_EDMA3_MEMPROTECT                0
#endif