AM335x DMTIMER PWM Generation

g.f.

Guru 15510 points

Hi,

I have question about AM335x DMTIMER.

My customer are using DMTIMER6 to generate PWM pulse(4096Hz or 4219Hz)

Case 1: generate 4096Hz

When they use CLK_32KHz as DMTIMER clock source and configure the DMTIMER register as following,

4096Hz was output successfully.

/////////////////////////////////////////////////////////////////////////

CLKSEL_TIMER6_CLK = 0x00000002 //select CLK_32KHz

CM_PER_TIMER6_CLKCTRL = 0x00000002 //Enable

TIMER6_TCLR = 0x00000040 // PT=0,TRG=0,SCPWM=0,CE=1,PRE=0,PTV=0,AR=0,ST=0

TIMER6_TMAR = 0xFFFFFFFB

TIMER6_TLDR = 0xFFFFFFF8

TIMER6_TTGR = 0x00000000

/////////////////////////////////////////////////////////////////////////

Case 2: generate 4219Hz

But when they use CLK_M_OSC(24MHz) as DMTIMER clock source and configure the DMTIMER register as following,

they don't know why but it output about 32KHz.

/////////////////////////////////////////////////////////////////////////

CLKSEL_TIMER6_CLK = 0x00000001 //select CLK_M_OSC(24MHz)

CM_PER_TIMER6_CLKCTRL = 0x00000002 //Enable

TIMER6_TCLR = 0x00000068 //PT=0,TRG=0,SCPWM=0,CE=1,PRE=1,PTV=010,AR=0,ST=0

TIMER6_TMAR = 0xFFFFFE9C

TIMER6_TLDR = 0xFFFFFD39

TIMER6_TTGR = 0x00000000

/////////////////////////////////////////////////////////////////////////

In case 2, I guess register configuration is fine.

From the configuration value of TCLR.PRE, TCLR.PTV, TLDR, I guess about 4220Hz should be generated.

If the register configurations are mistaken, can you please tell me.

best regards,

g.f.

over 10 years ago

0 Yordan Kovachev over 10 years ago

TI__Guru**** 161600 points

Hi g.f.,

g.f. said:
From the configuration value of TCLR.PRE, TCLR.PTV, TLDR, I guess about 4220Hz should be generated.

Yes, you are correct, according to Section 20.1.3.6 Timer Counting Rate they should get 4219,4Hz out of this configuration.

Can you share, which SDK did they use to test this? I will try to reproduce this on my side.

Best Regards,
Yordan

0 g.f. over 10 years ago in reply to Yordan Kovachev

Guru 15510 points

Hi Yordan,

Thank you for the reply.

They are not using SDK.
They configured the DMTIMER register from GEL file as follow:

hotmenu DMTIMER6_4096Hz()
{
WR_MEM_32(CLKSEL_TIMER6_CLK ,0x00000002); // Select CLK_32KHz(32768Hz)
WR_MEM_32(CM_PER_TIMER6_CLKCTRL,0x00000002); // Enable
WR_MEM_32( TIMER6_TCLR ,0x00000040); // PT=0,TRG=0,SCPWM=0,CE=1,PRE=0,PTV=0,AR=0,ST=0
WR_MEM_32( TIMER6_TMAR ,0xFFFFFFFB); // duty = 50%
WR_MEM_32( TIMER6_TLDR ,0xFFFFFFF8);
WR_MEM_32( TIMER6_TTGR ,0x00000000);
}

hotmenu DMTIMER6_4219Hz()
{
WR_MEM_32(CLKSEL_TIMER6_CLK ,0x00000001); // Select CLK_M_OSC(24MHz)
WR_MEM_32(CM_PER_TIMER6_CLKCTRL,0x00000002); // Enable
WR_MEM_32( TIMER6_TCLR ,0x00000068); // PT=0,TRG=0,SCPWM=0,CE=1,PRE=1,PTV=010,AR=0,ST=0
WR_MEM_32( TIMER6_TMAR ,0xFFFFFE9C); // duty = 50.07%
WR_MEM_32( TIMER6_TLDR ,0xFFFFFD39);
WR_MEM_32( TIMER6_TTGR ,0x00000000);
}

best regards,
g.f.

0 Yordan Kovachev over 10 years ago in reply to g.f.

TI__Guru**** 161600 points

Hi,

I tested on my beaglebone black, running SDK1, kernel 3.14.26-g2489c02.

For testing, I used the following user space scripts:

test.sh.txt

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#!/bin/sh
for i in {1..20}
do 
./timer.sh
done
#END
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

#!/bin/sh

for i in {1..20}

do 

./timer.sh

done

#END

timer.sh.txt

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#!/bin/sh
# timer_run.sh
#
# This script configures Timer4 to be run
# on the VP1 Board. After configured,
# the timer runs indefinitely at a fixed
# freq and duty cycle, fed from the
# internal CLK_M_OSC clock
#
echo "Configuring Timer 6...\n"
#configurations changed for Timer6
# Enable Timer4's clock in CM_PER
# This allows us to access it's control regs
#devmem2 0x44e00088 w 0x2
# Set the Pinmux for Timer4 (0x2 because its mode 2 of this pin)
# Using the pin mux linux driver from the SDK
# echo 0x22 > /sys/kernel/debug/omap_mux/xdma_event_intr0
#Select TIMER6 CLOCK SOURCE
devmem2 0x44e0051c w 0x1
#Enable timer to access its ctrl regs
devmem2 0x44e000f0 w 0x2
# Timer configurations.. Stop Timer.
# Auto-Reload
# Compare Mode Enabled
# Trigger set on overflow
# Toggle Mode
#devmem2 0x48044038 w 0x1842
devmem2 0x48048038 w 0x68
# Write to the CM_DPLL registers to select the clk source
# Selected the clk source for the Timer4
# This should be &= (default 0x12) (writing a 0x2 for 32kHz)
#0x1 = SEL2 : Select CLK_M_OSC clock
#devmem2 0x44e00510 w 0x1
#devmem2 0x44e0051c w 0x1
# Initial count value
#devmem2 0x4804403C w 0xFFFFAFFF
# Set the re-load value
#devmem2 0x48044040 w 0xFFFFDFFF
devmem2  0x48048040 w 0xFFFFFD39
# Setting a duty cycle to 50.7%
#devmem2 0x4804404C w 0xFFFFFAF0
devmem2 0x4804804c w 0xFFFFFE9C
#set trigger
devmem2 0x48048044 w 0x00000000
# Force the Timer to Smart-Idle
#devmem2 0x48044010 w 0x8
devmem2 0x48048010 w 0x8
# Start Timer
devmem2 0x48048038 w 0x186B
# Verify that the timer is running,
# by polling the count register a
# few times. We should we up counting.
for i in {1..2}
do
 echo "Timer Value $i"
 devmem2 0x4804803C
# End
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

#!/bin/sh

# timer_run.sh
#
# This script configures Timer4 to be run
# on the VP1 Board. After configured,
# the timer runs indefinitely at a fixed
# freq and duty cycle, fed from the
# internal CLK_M_OSC clock
#

echo "Configuring Timer 6...\n"
#configurations changed for Timer6
# Enable Timer4's clock in CM_PER
# This allows us to access it's control regs
#devmem2 0x44e00088 w 0x2

# Set the Pinmux for Timer4 (0x2 because its mode 2 of this pin)
# Using the pin mux linux driver from the SDK
# echo 0x22 > /sys/kernel/debug/omap_mux/xdma_event_intr0

#Select TIMER6 CLOCK SOURCE
devmem2 0x44e0051c w 0x1
#Enable timer to access its ctrl regs
devmem2 0x44e000f0 w 0x2

# Timer configurations.. Stop Timer.
# Auto-Reload
# Compare Mode Enabled
# Trigger set on overflow
# Toggle Mode
#devmem2 0x48044038 w 0x1842
devmem2 0x48048038 w 0x68

# Write to the CM_DPLL registers to select the clk source
# Selected the clk source for the Timer4
# This should be &= (default 0x12) (writing a 0x2 for 32kHz)
#0x1 = SEL2 : Select CLK_M_OSC clock
#devmem2 0x44e00510 w 0x1
#devmem2 0x44e0051c w 0x1
# Initial count value
#devmem2 0x4804403C w 0xFFFFAFFF

# Set the re-load value
#devmem2 0x48044040 w 0xFFFFDFFF
devmem2  0x48048040 w 0xFFFFFD39
# Setting a duty cycle to 50.7%
#devmem2 0x4804404C w 0xFFFFFAF0
devmem2 0x4804804c w 0xFFFFFE9C

#set trigger
devmem2 0x48048044 w 0x00000000
# Force the Timer to Smart-Idle
#devmem2 0x48044010 w 0x8
devmem2 0x48048010 w 0x8
# Start Timer
devmem2 0x48048038 w 0x186B

# Verify that the timer is running,
# by polling the count register a
# few times. We should we up counting.
for i in {1..2}
do
 echo "Timer Value $i"
 devmem2 0x4804803C

# End
echo "Timer is Running!"
echo ""
echo "See TP31 on the EVM"
echo ""

# Delay added to allow time for the first timer
# overflow to occur, before any consecutive memory
# accesses are made. (Just for standby testing).

sleep 1

done

# Disable MODULEMODE of CM_PER_TIMER4_CLKCTRL register
# Only if this value is 0, are we able to wake-up from standby??
devmem2 0x44e000f0 w 0x0

#END

I place the scripts in /home/root and execute ./test.sh

As a result my scope showed 4.2khz, which equals the calculated result (using formulas in Section 20.1.3.6 Timer Counting Rate).

Can you please confirm from your side?

Best Regards,
Yordan

0 g.f. over 10 years ago in reply to Yordan Kovachev

Guru 15510 points

Hi Yordan,

Thank you for the reply and I'm sorry for the delay.
I tried with the value you attached and the output signal was about 4.2kHz.

You set the TCLR register bit[12] PT to '1'(toggle), but I want to set PT to '0'(Pulse).
I guess my TCLR register value is wrong so it can't output 4200Hz. But I don't know which bit field is wrong.
Is there any sample which are using Pulse mode?

best regards,
g.f.

0 Yordan Kovachev over 10 years ago in reply to g.f.

TI__Guru**** 161600 points

Hi g.f.

Can you try the following code:

timer.txt

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#!/bin/sh
# timer_run.sh
#
# This script configures Timer4 to be run
# on the VP1 Board. After configured,
# the timer runs indefinitely at a fixed
# freq and duty cycle, fed from the
# internal CLK_M_OSC clock
#
echo "Configuring Timer 6...\n"
#configurations changed for Timer6
# Enable Timer4's clock in CM_PER
# This allows us to access it's control regs
#devmem2 0x44e00088 w 0x2
# Set the Pinmux for Timer4 (0x2 because its mode 2 of this pin)
# Using the pin mux linux driver from the SDK
# echo 0x22 > /sys/kernel/debug/omap_mux/xdma_event_intr0
#Select TIMER6 CLOCK SOURCE
devmem2 0x44e0051c w 0x1
#Enable timer to access its ctrl regs
devmem2 0x44e000f0 w 0x2
# Timer configurations.. Stop Timer.
# Auto-Reload
# Compare Mode Enabled
# Trigger set on overflow
# Toggle Mode
#devmem2 0x48044038 w 0x1842
devmem2 0x48048038 w 0x68
# Write to the CM_DPLL registers to select the clk source
# Selected the clk source for the Timer4
# This should be &= (default 0x12) (writing a 0x2 for 32kHz)
#0x1 = SEL2 : Select CLK_M_OSC clock
#devmem2 0x44e00510 w 0x1
#devmem2 0x44e0051c w 0x1
# Initial count value
#devmem2 0x4804403C w 0xFFFFAFFF
# Set the re-load value
#devmem2 0x48044040 w 0xFFFFDFFF
devmem2  0x48048040 w 0xFFFFFD39
# Setting a duty cycle to 50.7%
#devmem2 0x4804404C w 0xFFFFFAF0
devmem2 0x4804804c w 0xFFFFFE9C
#set trigger
devmem2 0x48048044 w 0x00000000
# Force the Timer to Smart-Idle
#devmem2 0x48044010 w 0x8
devmem2 0x48048010 w 0x8
# Start Timer
devmem2 0x48048038 w 0x86F
# Verify that the timer is running,
# by polling the count register a
# few times. We should we up counting.
#for i in {1..2}
#do
 echo "Timer Value $i"
 devmem2 0x4804803C
# End
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

#!/bin/sh

# timer_run.sh
#
# This script configures Timer4 to be run
# on the VP1 Board. After configured,
# the timer runs indefinitely at a fixed
# freq and duty cycle, fed from the
# internal CLK_M_OSC clock
#

echo "Configuring Timer 6...\n"
#configurations changed for Timer6
# Enable Timer4's clock in CM_PER
# This allows us to access it's control regs
#devmem2 0x44e00088 w 0x2

# Set the Pinmux for Timer4 (0x2 because its mode 2 of this pin)
# Using the pin mux linux driver from the SDK
# echo 0x22 > /sys/kernel/debug/omap_mux/xdma_event_intr0

#Select TIMER6 CLOCK SOURCE
devmem2 0x44e0051c w 0x1
#Enable timer to access its ctrl regs
devmem2 0x44e000f0 w 0x2

# Timer configurations.. Stop Timer.
# Auto-Reload
# Compare Mode Enabled
# Trigger set on overflow
# Toggle Mode
#devmem2 0x48044038 w 0x1842
devmem2 0x48048038 w 0x68

# Write to the CM_DPLL registers to select the clk source
# Selected the clk source for the Timer4
# This should be &= (default 0x12) (writing a 0x2 for 32kHz)
#0x1 = SEL2 : Select CLK_M_OSC clock
#devmem2 0x44e00510 w 0x1
#devmem2 0x44e0051c w 0x1
# Initial count value
#devmem2 0x4804403C w 0xFFFFAFFF

# Set the re-load value
#devmem2 0x48044040 w 0xFFFFDFFF
devmem2  0x48048040 w 0xFFFFFD39
# Setting a duty cycle to 50.7%
#devmem2 0x4804404C w 0xFFFFFAF0
devmem2 0x4804804c w 0xFFFFFE9C

#set trigger
devmem2 0x48048044 w 0x00000000
# Force the Timer to Smart-Idle
#devmem2 0x48044010 w 0x8
devmem2 0x48048010 w 0x8
# Start Timer
devmem2 0x48048038 w 0x86F

# Verify that the timer is running,
# by polling the count register a
# few times. We should we up counting.
#for i in {1..2}
#do
 echo "Timer Value $i"
 devmem2 0x4804803C

# End
echo "Timer is Running!"
echo ""
echo "See TP31 on the EVM"
echo ""

# Delay added to allow time for the first timer
# overflow to occur, before any consecutive memory
# accesses are made. (Just for standby testing).

sleep 1

#done

# Disable MODULEMODE of CM_PER_TIMER4_CLKCTRL register
# Only if this value is 0, are we able to wake-up from standby??
devmem2 0x44e000f0 w 0x0

#END

Using these settings I was able to get 4.169KHz on the scope.

I was executing ./timer.sh in order to do the measurement.

When in pulse mode, I had to change the PTV bit field to 3, in order to achieve 4.169KHz. Using PTV=2 the frequency on the TIMER6 output pin was 8kHz. Not sure why timer is behaving like this.

Best Regards,
Yordan

0 g.f. over 10 years ago in reply to Yordan Kovachev

Guru 15510 points

Hi Yordan,

Thank you for the reply.
Sorry, I'm out of office today, so I will try tomorrow.

best regards,
g.f.

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AM335x DMTIMER PWM Generation