AM335x DDR3 400MHz SW leveling issue

Lo2

Expert 1935 points

Other Parts Discussed in Thread: TPS51200, AM3358

Hello,

My AM335x is connected to a single 16bit-DDR3 chip, the Vtt is generated by a voltage divider.

My system starts up and boots linux just fine using the beagleboneblack DDR3 u-boot settings.

Now I'd like to check and optimize my DDR3 settings but the software leveling fails.

I follow the instructions from the wiki: http://processors.wiki.ti.com/index.php/AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling

But the S/W leveling only reports zeros:

[CortxA8]
Enter the PHY_INVERT_CLKOUT value (0 or 1) from the spreadsheet
1

Enter the Seed RD_DQS_SLAVE_RATIO Value in Hex to search the RD DQS Ratio Window
80

Enter the Seed FIFO_WE_SLAVE_RATIO Value in Hex to search the RD DQS Gate Window
40

Enter the Seed WR_DQS_SLAVE_RATIO Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
F8

***************************************************************
   The Slave Ratio Search Program Values are...
***************************************************************
PARAMETER                       MAX | MIN | OPTIMUM | RANGE
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO    0x000 | 0x000 | 0x000 | 0x000
DATA_PHY_FIFO_WE_SLAVE_RATIO   0x000 | 0x000 | 0x000 | 0x000
DATA_PHY_WR_DQS_SLAVE_RATIO    0x000 | 0x000 | 0x000 | 0x000
DATA_PHY_WR_DATA_SLAVE_RATIO   0x000 | 0x000 | 0x000 | 0x000
***************************************************************
rd_dqs_range = 0
fifo_we_range = 0
wr_dqs_range = 0
wr_data_range = 0

Optimal values have been found!!

***************************************************************
   The Slave Ratio Search Program Values are...
***************************************************************
PARAMETER                       MAX | MIN | OPTIMUM | RANGE
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO    0x000 | 0x000 | 0x000 | 0x000
DATA_PHY_FIFO_WE_SLAVE_RATIO   0x000 | 0x000 | 0x000 | 0x000
DATA_PHY_WR_DQS_SLAVE_RATIO    0x000 | 0x000 | 0x000 | 0x000
DATA_PHY_WR_DATA_SLAVE_RATIO   0x000 | 0x000 | 0x000 | 0x000
***************************************************************

===== END OF TEST =====

This is similar to this post: https://e2e.ti.com/support/arm/sitara_arm/f/791/t/379997#pi316653=3

But I have not GPIO to switch Vtt.

Please find attached a spreadsheet with all my settings (SDRAM_TIM_xxx) and calculations (ratio search)

Memory: MT41K128M16JT-125:K FBGA CODE D9PTK datasheet: http://www.micron.com/~/media/documents/products/data-sheet/dram/ddr3/2gb_1_35v_ddr3l.pdf

Is there a way to modify the GEL file or procedure so I can do DDR3 SW/ leveling?

Regards,

Lo2

over 9 years ago

0 Brad Griffis over 9 years ago

TI__Guru*** 125430 points

Are you confusing Vtt and VREF? Vtt is for parallel termination of the address and control lines. VREF is usually generated with a divider. For a 16-bit DDR3 device there is no need for parallel termination. If you are truly using parallel termination, this cannot be done with a resistor divider. You need a special device like the TPS51200 for this purpose that is capable of sourcing and sinking current.

0 Lo2 over 9 years ago in reply to Brad Griffis

Expert 1935 points

Hello Brad,

true, Vref is set by a voltage divider.

I've got no Vtt.

Here are my timing calulations/settings:

MT41K128M16JT-125_K_FBGA_CODE_ D9PTK.ods.zip

Regards,

0 Lo2 over 9 years ago in reply to Lo2

Expert 1935 points

Hi Brad,

If I start uboot (to set my DDR3 config), connect via JTAG (XDS200) to my board I can run the data integrity checks:

CortxA8: GEL Output: Try Accessing DDR memory....Write data
CortxA8: GEL Output: Data written at :: 0x80000000
CortxA8: GEL Output: Data written at :: 0x80000004
[....]
CortxA8: GEL Output: No of Failed locations are :: 0x00000000
CortxA8: GEL Output: No of Failed locations are :: 0x00000000
CortxA8: GEL Output: Data Integrity check Passed

If I then run the AM338x initialization from the GEL script an rerun the data integrity checks, all fails:

CortxA8: Output: **** AM3358_SK Initialization is in progress ..........
CortxA8: Output: **** AM335x ALL PLL Config for OPP == OPP100 is in progress .........
CortxA8: Output: Input Clock Read from SYSBOOT[15:14]: 25MHz
CortxA8: Output: **** AM335x PLL Config failed!! Check SYSBOOT[15:14] for proper input freq config
CortxA8: Output: **** AM335x DDR3 EMIF and PHY configuration is in progress...
CortxA8: Output: EMIF PRCM is in progress .......
CortxA8: Output: EMIF PRCM Done
CortxA8: Output: DDR PHY Configuration in progress
CortxA8: Output: Waiting for VTP Ready .......
CortxA8: Output: VTP is Ready!
CortxA8: Output: DDR PHY CMD0 Register configuration is in progress .......
CortxA8: Output: DDR PHY CMD1 Register configuration is in progress .......
CortxA8: Output: DDR PHY CMD2 Register configuration is in progress .......
CortxA8: Output: DDR PHY DATA0 Register configuration is in progress .......
CortxA8: Output: DDR PHY DATA1 Register configuration is in progress .......
CortxA8: Output: Setting IO control registers.......
CortxA8: Output: EMIF Timing register configuration is in progress .......
CortxA8: Output: EMIF Timing register configuration is done .......
CortxA8: Output: PHY is READY!!
CortxA8: Output: DDR PHY Configuration done
CortxA8: Output: **** AM3358_SK Initialization is Done ******************

CortxA8: GEL Output: Try Accessing DDR memory....Write data
CortxA8: GEL Output: Data written at :: 0x80000000
CortxA8: GEL Output: Data written at :: 0x80000004
[...]
CortxA8: GEL Output: No of Failed locations are :: 0x000000F8
CortxA8: GEL Output: No of Failed locations are :: 0x000000F9
CortxA8: GEL Output: Data Integrity check Failed

Which register settings should I check?

Regards,
Lo2

0 Biser Gatchev-XID over 9 years ago in reply to Lo2

TI__Guru**** 393215 points

It seems that your clock frequency is 25MHz. The GEL initialization is for 24MHz.

0 Biser Gatchev-XID over 9 years ago in reply to Biser Gatchev-XID

TI__Guru**** 393215 points

See this post for details: e2e.ti.com/.../1583576

0 Lo2 over 9 years ago in reply to Lo2

Expert 1935 points

Just to check my calculated register settings, I've set them manually in U-Boot and with those settings it will boot linux too.

Dump old BBB settings:
U-Boot# md 0x4C000000
4c000000: 40443403 40000000 61c05332 00000000 .4D@...@2S.a....
4c000010: 00000c30 00000c30 0aaad4db 0aaad4db 0...0...........
4c000020: 266b7fda 266b7fda 501f867f 501f867f ..k&..k&...P...P
4c000030: 00000000 00000000 00000000 00000000 ................
4c000040: 00000000 00000000 00000000 00000000 ................
4c000050: 00000000 00ffffff 8000140a 00021616 ................
4c000060: 00002011 00000000 00000000 00000000 . ..............
4c000070: 00000000 00000000 00000000 00000000 ................
4c000080: 0069aae8 001afb1c 00010000 00000000 ..i.............
4c000090: 0979f933 00000000 00050000 00050000 3.y.............
4c0000a0: 00000000 00000000 00000000 00000000 ................
4c0000b0: 00000000 00000000 00000000 00000000 ................
4c0000c0: 00000000 00000000 50074be4 00000000 .........K.P....
4c0000d0: 00000000 00000000 00000000 00000000 ................
4c0000e0: 00000000 00100007 00100007 00000000 ................
4c0000f0: 00000000 00000000 00000000 00000000 ................

Modify some SDRAM/DDR3 registers:
mw.l 0x4C0000e4 0x00100008
mw.l 0x4C0000e8 0x00100008
mw.l 0x4C000008 0x61c05932
mw.l 0x4C000010 0x00000C30
mw.l 0x4C000014 0x00000C30
mw.l 0x4C000018 0x0AAAD4DB
mw.l 0x4C00001c 0x0AAAD4DB
mw.l 0x4C000020 0x38377FE3
mw.l 0x4C000024 0x38377FE3
mw.l 0x4C000028 0x501F833F
mw.l 0x4C00002c 0x501F833F

Check if settings were successful:
U-Boot# md 0x4c000000
4c000000: 40443403 40000004 61c05932 00000000 .4D@...@2Y.a....
4c000010: 00000c30 00000c30 0aaad4db 0aaad4db 0...0...........
4c000020: 38377fe3 38377fe3 501f833f 501f833f ..78..78?..P?..P
4c000030: 00000000 00000000 00000000 00000000 ................
4c000040: 00000000 00000000 00000000 00000000 ................
4c000050: 00000000 00ffffff 8000140a 00021616 ................
4c000060: 00002011 00000000 00000000 00000000 . ..............
4c000070: 00000000 00000000 00000000 00000000 ................
4c000080: 005ce19e 001a2388 00010000 00000000 ..\..#..........
4c000090: 2a5ef132 00000000 00050000 00050000 2.^*............
4c0000a0: 00000000 00000000 00000000 00000000 ................
4c0000b0: 00000000 00000000 00000000 00000000 ................
4c0000c0: 00000000 00000000 50074be4 00000000 .........K.P....
4c0000d0: 00000000 00000000 00000000 00000000 ................
4c0000e0: 00000000 00100008 00100008 00000000 ................
4c0000f0: 00000000 00000000 00000000 00000000 ................

Ok, try to boot linux:

U-Boot#setenv bootargs 'console=ttyO0,115200n8 root=/dev/mmcblk0p2 ro rootfstype=ext4 rootwait'
U-Boot#load mmc 0 ${fdtaddr} heivapind_arm.dtb
U-Boot#load mmc 0 ${loadaddr} zImage
U-Boot#bootz ${loadaddr} - ${fdtaddr};
reading zImage
3590808 bytes read in 333 ms (10.3 MiB/s)
U-Boot# bootz ${loadaddr} - ${fdtaddr};
Kernel image @ 0x80200000 [ 0x000000 - 0x36ca98 ]
## Flattened Device Tree blob at 80f80000
Booting using the fdt blob at 0x80f80000
Using Device Tree in place at 80f80000, end 80f8b45b

Starting kernel ...

[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 3.12.10 (lf@xeon) (gcc version 4.9.3 (Buildroot 2015.08.1) ) #6 PREEMPT Tue Nov 10 23:31:06 CET 2015
[ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] Machine: Generic AM33XX (Flattened Device Tree), model: TI AM335x BeagleBone
[ 0.000000] Memory policy: ECC disabled, Data cache writeback
[ 0.000000] CPU: All CPU(s) started in SVC mode.
[ 0.000000] AM335X ES2.1 (sgx neon )
[...]
boots to login prompt and I can use the system.

When I start u-boot, modify the memory controller settings (as shown above) I can connect to the target via JTAG. I skip the GEL file based initialization and immediately load and start the slave_ratio_search binary. Still it reports only zeros.

Is the source code to the slave ratio search binary available?

Regards,
Lo

0 Lo2 over 9 years ago in reply to Biser Gatchev-XID

Expert 1935 points

Hi Biser,

thanks that was exaclty the patch for the GEL file I needed!

Best regards,

Lo2

For reference, add the following code to the GEL file:

In the 'hotmenu ARM_OPP100_Config()' section add:

else if(CLKIN==25)
{
   MPU_PLL_Config( CLKIN, 24, 500, 1);
   CORE_PLL_Config( CLKIN, 24, 500, 10, 8, 4);
// DDR3 400MHz setting
// DDR_PLL_Config( CLKIN, 24, 400, 1);
// DDR3 303MHz setting
   GEL_TextOut("**** Setting DDR PLL to 303MHz ......... \n","Output",1,1,1);
   DDR_PLL_Config( CLKIN, 24, 303, 1);
   PER_PLL_Config( CLKIN, 24, 960, 5);
   DISP_PLL_Config( CLKIN, 24, 48, 1);
   GEL_TextOut("**** AM335x ALL ADPLL Config for OPP == OPP100, 25MHz input is Done ......... \n","Output",1,1,1);
}

0 Brad Griffis over 9 years ago in reply to Lo2

TI__Guru*** 125430 points

Lo2 -- thanks for sharing the code snippet. I'm sure that will help others on the community.

0 Lo2 over 9 years ago in reply to Lo2

Expert 1935 points

Additional fix for 1GHz AM335x:

CORE_PLL_Config( CLKIN, 24, 500, 10, 8, 4);

should be

CORE_PLL_Config( CLKIN, 24, 1000, 10, 8, 4);

for a 1GHz CPU.

My gel file for convenience:

AM3358_StarterKit_Patch25MHz_MyDDR3.gel

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AM335x DDR3 400MHz SW leveling issue