TMS320C5517: C5517, can I drive CLK_IN at 18.432MHz?

Brad Caldwell

Part Number: TMS320C5517

Hi,

Due to legacy circuitry, I want to drive CLK_IN of the C5517 at 18.432MHz. This same clock will drive an AIC3104 CODEC.

I know this frequency doesn't match any of the ones the boot ROM code expects.However, I'll be booting from SPI flash and if I set my BootModes[5:0]=110110 (CLK_SEL=19.2 via CLK_IN, SPI flash boot) so having an exact frequency doesn't matter that much if I'm off by 5%.

So my question is, is this okay? I'll be using I2C and McBSP at runtime but will program the dividers accordingly assuming an 18.432 input.

As long as I can program all my peripherals after boot to be what I want, are there any other reasons why I can't do this? Is the device characterized at the range of frequencies between 12 and 19.2 or is it only characterized at the select CLK_IN frequency points?

The datasheet wording isn't crisp enough to say I absolutely have to use on of the selected frequencies and nothing in between.

over 7 years ago

0 Yordan Kovachev over 7 years ago

TI__Guru**** 161600 points

Hi Brad,

In my opinion you need to be in one of the frequencies listed in the datasheet. See Section 5.7.4.3.3.3 CLKIN Pin With LVCMOS-Compatible Clock Input (Optional) as well as Table 5-10. Timing Requirements for CLKIN from the Datasheet:
"The bootloader assumes that the CLKIN pin is connected to the LVCMOS-compatible clock source with frequency of 11.2896, 12.0, 12.288, 16.8, or 19.2 MHz based on the value of BootMode[5:4] bits at reset."

I am also looping the design team to elaborate if necessary.

Best Regards,
Yordan

0 Brad Caldwell over 7 years ago in reply to Yordan Kovachev

TI__Genius 12595 points

Yes, if possible, please have the design team comment. Is the restriction there simply because of the boot ROM to ensure the peripherals are clocked at the correct frequency at boot time or for other reasons? If it's simply because of the boot ROM, then I don't care because I'm booting from SPI flash.

0 Mark M over 7 years ago in reply to Brad Caldwell

TI__Mastermind 30140 points

Hi Brad,

Check out the C5517 PLL calculator with Bootloader PLL config on this thread: https://e2e.ti.com/support/dsp/c5000/f/109/p/670409/2473205#2473205

For all SPI boot modes, the bootloader multiplies the input clock by three, and the PLL settings must not exceed the maximum frequencies for the PLL (See Table 5-7. PLL Clock Frequency Ranges in the C5517 datasheet).

I calculated a maximum CLKIN of 26MHz will keep the PLL within range. Of course the SPI CLK will scale accordingly.

To give you a taste, I ran the numbers for a customer who was booting from McSPI. You can see the different SPI frequencies given a range of CLKIN frequencies.

/cfs-file/__key/communityserver-discussions-components-files/791/4812.5023.McSPI-boot-clock-speeds-with-audio-clocks-for-CLKIN.xlsx

Notice that you can even fool the bootloader by telling it false information through the bootmode[5:4] pins...

Of course, all this is bending the rules of the datasheet a little bit, so make sure to provide a disclaimer.

Hope this helps,
Mark

0 Brad Caldwell over 7 years ago in reply to Mark M

TI__Genius 12595 points

Mark, thanks for the detailed response, just what I was looking for.

Processors

Processors forum

TMS320C5517: C5517, can I drive CLK_IN at 18.432MHz?