AM5728: PCIe external clock SI issues

Hi John,
Is any of what you've observed causing a specific issue in your implementation(s) of the AM57xx device?

No, we have not seen any specific issues arise because of this yet.

It is a concern of our customer using our module, and we wanted to determine the cause of this to verify whether or not this would become an issue long term.

It just raises some concerns about the clock being stable over time/temperature/etc...

Johnathan,

Please provide the schematic for the latest implementation that you reference.  Please provide captures of the oscilloscope image initially and after it becomes invalid.  Also indicate on the schematic the point where the scope probes are attached.

Tom

Tom,

Here is the external clock generator circuit (using a PI6C557-03):

And here is the input at the AM57x, I am probing with a Tektronix P6248 differential probe at the points indicated by the red arrows/circles (at the driver side of the coupling capacitors). Note that the signal names are slightly different since they are on separate board schematics, but X_PCIE_REFCLKN / X_PCIE_REFCLKP are connected to X_REFCLKN / X_REFCLKP from the external clock generator:

Here is the initial waveform right at power-up:

And here is the waveform at the same probe location after some time (~10-15 seconds or so):

While this hasn't caused any functional issues yet, we would like to understand why this is happening and if we can revise anything in our design to stabilize the clock signal. We just don't want this to develop into an issue at some point down the road. Initially we figured the DC bias was blocked anyway and would only pass along the AC component to the LJCB inputs, so maybe this is fine. However, it seems a probe load connected briefly at R206 will cause the signal to return to 'normal' when measured right afterwards. So when we probe the clock across the 100 ohm termination resistor (R206) in the schematic above (receiver side of the AC coupling caps) it appears the clock signal is clean and not distorted. But I am concerned that maybe the probe is affecting the circuit and causing it to appear fine even though it may also be distorted at the LJCB inputs once the probe is removed. I am not confident in this assumption, but just a thought.

Any feedback about this would be much appreciated.

Regards,

John

John,

You stated that the PI6C557-03 provides a standard, compliant, HCSL signal.  The termination resistors appear to confirm that this is a compliant HCSL signal.  If so, then the distorted signal must be the result of the way the scope is configured.  To confirm this, I recommend that you measure this clock output without the AM57xx attached.  You can do this by removing C136 and C137 while keeping everything else unchanged.  Since this also removes the 100 ohm termination at the load, the signal will be somewhat larger but there should be no distortion and no change over time.

Tom

Tom,

When removing the capacitors and measuring the signal it remains stable and does not distort over time, as you said. But are you sure that this confirms that the scope is the cause of the issue? Couldn't it still be possible that the capacitors in combination with the internal circuitry of the LJCB inputs could be contributing to this? Right at power-up of the system, the the signal looks fine with the scope probe connected. Additionally, if you wait for some time before connecting the probe you will see the distortion immediately which seems to suggest that the signal isn't slowly distorting because of the probe load.

In the case of the TI EVM, the same distortion was measured using an external LVDS clock (from what I recall from the previous thread). Did you determine the reason this was being measured on the TI system as well? Any specifics on what might be happening with the scope/probe?

Regards,
John Feuerstein

John,

If the distortion never occurs with the capacitors removed, then it is not a scope issue.

Please provide single-ended scope captures rather than differential both before and after the distortion occurs.  Be sure to have the VSS point shown in the captures.

Tom

Tom,

Ah I understand what you meant now, sorry about that. See below for captures of X_PCIE_REFCLKP, measuring with a single-ended probe (referenced to GND) at the driver side of C137.

Initially at power-up:

And the same X_PCIE_REFCLKP location after some time (~10-15 seconds):

The same is measured for X_PCIE_REFCLKN as well. Do you need anything else beyond this?

Thanks,

John

John,
Where is ground in these captures? Is it the middle line? The display says there is a 200mV offset. How is that comprehended in the display?
Tom

Tom,

Sorry, this offset setting was from earlier measurements and I forgot to remove it. In these captures ground is the middle line. Here are some new captures with Vss labeled:

Initial:

After some time:

-John

John,

Please also provide scope captures on the load side of the capacitors both before and after the distortion occurs.  Does the addition of the scope probe on the load side change the behavior?

Tom

Tom,

Here is a capture across the R206 resistor on the load side using a differential probe:

And here is a single-ended capture (same Vss at the middle line) of REFCLK at the LJCB_CLKP pin:

I do not see any distortion when measuring on the load side of the capacitors, the clock remains stable at the processor inputs. Even though I don't notice a difference on the load-side caused by the probe, if I touch any probe tip to either side of R206 then the signal on the driver side of the capacitors shifts from distorted back to 'normal'. Once I remove the probe from the load side, the driver side will again shift back to the distorted waveform.

Initially this is why I thought it wouldn't be an issue since the load-side appears to be fine. But I am wondering if the probe loading is causing the signal to appear fine, and perhaps it distorts as soon as I remove it. Though I am not sure how to verify that...

Regards,

John

John,

Do you see this behavior on all board or only a percentage of the boards tested?  How many have you produced?

Tom

 

Tom,

Yes, so far I have seen this behavior on all boards. I have probed ~10 units and each one has shown similar distortion.

Looking back at the single-ended captures I found it interesting that there was a ~200mV offset... When testing the removal of the capacitors before, I noticed this offset was not present and that the signal level was at the expected HCSL levels.  Here is a screen capture of a single-ended measurement of the same X_PCIE_REFCLKP net with the C136 and C137 capacitors removed:

I also noticed that the single-ended measurement on the load side I posted earlier shows a negative ~200mV offset. Is this expected or should it also be at HCSL levels (0-750mV)? I am just wondering if this may provide some hints as to what is going on... Are you able to produce similar measurements on the TI EVM? Curious how the LVDS behavior would compare to HCSL.

John

John,

The PCIe clock input contains a 100-ohm termination.  What do you see when the capacitors are installed but the 100-ohm termination is removed?

I have initiated a discussion with the IP designer to understand how this can be happening.

Tom

Tom,

See below for updated measurements with R206 removed.

Differential measurement of driver-side immediately at power-up:

 

Single-ended measurement of driver-side X_PCIE_REFCLKP immediately at power-up:

 

Differential measurement of driver-side after it becomes distorted:

 

Single-ended measurement of driver-side X_PCIE_REFCLKP after it becomes distorted:

 

Differential measurement of load-side:

 

Single-ended measurement of load-side REFCLK:

Regards,

John

John,

The 100-ohm differential termination is optional since the clock input has an internal 100-ohm termination.  Does the behavior change if this is removed?

Tom

Tom,

My last post shows the behavior when the 100-ohm resistor is removed. It still shows the same distortion and behavior, just some differences in the waveform characteristics.

-John

Tom,

I reworked a board to test your recommendation out. I used a 2.2MOhm pull-up to a 1.8V rail and a 1MOhm pull-down to ground. These were the most appropriate values I could find from what I have handy to meet your spec of 100k Thevenin resistance and DC level of ~0.5V. I also removed the 100-ohm R206 external resistor. 

This rework seems to have resolved the distortion issue. I just wanted to pass along this information as well as some screen captures in case that is of any help to you while you look into this internally. Please let me know if you come across any further information regarding this.

Below are some various measurements with the rework mentioned above applied to the REFCLK net (LJCB_CLKP input):

Differential measurement of driver-side: 

 

Single-ended measurement of driver-side X_PCIE_REFCLKP:

Single-ended measurement of driver-side X_PCIE_REFCLKN:

 

Differential measurement of load-side: 

Single-ended measurement of load-side REFCLK:

Single-ended measurement of load-side nREFCLK:

 

-John

Tom

And to follow up again, here are new captures when I apply that thevenin resistance rework to both LJCB input pins:

Differential measurement of load-side:

 

Single-ended measurement of load-side nREFCLK:

Single-ended measurement of load-side REFCLK:

 

Now both single-ended measurements do not fall below 0V, making the differential measurement more balanced.

-John

Tom,

What about the internal termination you mentioned, is the double termination necessary? Shouldn't the reference clock have ~ 0V to 0.7V single-ended swing? Adding this 100-ohm termination back cuts the signal amplitude in half and then it is no longer in that range. 

I also noticed that if I only add the Thevenin divider to one input, the other input will swing below 0V. Is this not an issue? It just seems like both inputs should be with the 0 to 0.7V single-ended swing for the HCSL/PCIe spec. Or am I misunderstanding something?

-John

Tom,

Thanks for clarifying. Sorry for all of the back and forth, just want to make sure we have all the information we need.

One more question. Before you said the external termination was not necessary: "The 100-ohm differential termination is optional since the clock input has an internal 100-ohm termination." Why would the internal termination not force a common mode level? Or is it a different type of termination (not across the input pins).

John