RTOS/AM5728: 2.5Mbps UART baudrate

Andreas Halbe

Part Number: AM5728

Tool/software: TI-RTOS

Hello,

I have a question regarding the UART baud-rate on a Sitara AM572x device. The table 24-149 & 24-150 inside the reference manual ‘spruhz6j.pdf’ shows the possible UART settings. My problem is, that I need to communicate with an encoder device, which supports only a baud-rate of 2.5[Mbps]. According to the tables the Sitara seems to support only 1.843[Mbps], 3.0[Mbps] and 3.6884[Mbps].

Carlo once created a post for us, which is slightly connected to this question:

https://e2e.ti.com/support/arm/sitara_arm/f/791/p/697553/2571837#2571837

I applied the formula from Rahul for the baud-rate of 2.5[Mbps] via using the two available oversampling rates 13 & 16, but the results also show me that 2.5[Mbps] may not be possible:

UART divider = Module clk /(overSamplingRate * baudrate)

UART divider = 48,000,000/(13*2,500,000) = 1.477 // Value too far away from an integer value
UART divider = 48,000,000/(16*2,500,000) = 1.2 // Value too far away from an integer value

The clock divider register, that holds just integer values, would create a deviation of the intended baud-rate in both cases.

Is there any chance that we can select 2.5[Mbps] as a UART baud-rate?

Thanks,

Andreas

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

Hi,

No, this cannot be done without significant error.

0 Biser Gatchev-XID over 7 years ago in reply to Biser Gatchev-XID

TI__Guru**** 393215 points

With an integer divide value of 1 you will get
48,000,000/(16*1)=3,000,000bps, which is off by 20% from desired baudrate, or
48,000,000/(13*1)=3,692,308bps, which is off by 47% from desired baudrate.

0 Andreas Halbe over 7 years ago in reply to Biser Gatchev-XID

Intellectual 455 points

Yes, and these baud-rates are of course mentioned inside the reference manual, so I assume the low level drivers support them right away. Thanks.

0 Andreas Halbe over 7 years ago in reply to Andreas Halbe

Intellectual 455 points

I have some additional questions regarding this topic. Inside the reference manual I see a table for a 48[MHz] UART input clock and one for 192[MHz] UART input clock.

Let us assume we somehow achieve using 192,000,000[MHz] as a UART input clock. If we now use an oversampling rate of 13, then the formula would be:

192,000,000 / (13*2,500,000) = 5.9077

The actual baud-rate would be: 192,000,000 / (6 * 13) = 2,461,538[bps]
The resulting error would be: (2,500,000 - 2,461,538) / 2,500,000 = 1.54%

I am not sure yet, but this might be OK for our purpose since we do not transmit too many contiguous bytes. We already changed the oversampling rate to 13 inside the UART library.

So my questions are:

a) Is it possible to select 192[MHz] as an UART input clock frequency?

b) Is the UART low level driver capable of dealing with a 192[MHz] input clock (identifying that this is the input clock frequency) or does the function always consider 48[MHz] as an input clock?

c) Would the low level driver function “UART_open_v1()” be able to set the value of 6 inside the UART.DLL & UART.DLH register or is the value of 5.9077 truncated to integer 5, which would introduce a bigger error?

If the above should be possible, then we need a clear instruction of how to change the UART library and the board library code in terms of changing the UART clock in order to achieve a baud-rate of 2,461,538[bps].

0 Rahul Prabhu over 7 years ago

TI__Guru** 116170 points

Andreas,

I would like to correct the response provided on this thread earlier. . The Table in the TRM is created for broad market UART users who typically use standard baud rates in their applications but that doesn`t limit non-baud rate users from using UART module divisor that are not in that table to get to the bit rates required.

For example: As I mentioned in the earlier response regarding baud rates, the bit rate is calculated as
UART bit rate = Module clk /(overSamplingRate * divisor)

In this case, if you are using 192 MHz module clock, then divider 6 will get you to 2.41 Mbps which is an error of 1.54%
UART bitrate = 192000000/(13*6) = 2.46 Mbps

Hence, we believe that this bit rate can be achieved with UART module on AM57x devices.

Regards,
Rahul

0 Rahul Prabhu over 7 years ago in reply to Andreas Halbe

TI__Guru** 116170 points

Looks like our responses were posted around the same time. As you have figured the UART bit rate can be set to 2.5MHz using 192 MHz module clock. Here are responses to additional questions:

Andreas Halbe said:
a) Is it possible to select 192[MHz] as an UART input clock frequency?

Yes, the UART input clock frequency can be set to 192 MHz.

Andreas Halbe said:
b) Is the UART low level driver capable of dealing with a 192[MHz] input clock (identifying that this is the input clock frequency) or does the function always consider 48[MHz] as an input clock?

The UART LLD driver source code reads the module clock setting from the hardware attributes(UART_HwAttrs) configured using UART_soc.c file in the driver or passed from the application and setting up the clocking itself is done using either GEL files or from board library. The MACRO CSL_UART_0_MODULE_FREQ that is used in the file is set to 48000000 in the file, pdk_am57xx_1_0_10\packages\ti\csl\soc\am572x\src\cslr_soc.h

The way the drivers are being tested by system test team in RTOS, it appears 48 MHz is the standard module clock used but the 192 Mhz settings have been tested by SOC validation teams as well as Linux teams and so there is no known issues with this configuration.

Andreas Halbe said:
c) Would the low level driver function “UART_open_v1()” be able to set the value of 6 inside the UART.DLL & UART.DLH register or is the value of 5.9077 truncated to integer 5, which would introduce a bigger error?

Once the board library/GEL sets up the module clock and you update the UART module clock in UART_soc.c, then the UART_open_v1 will use the formula that I mentioned to compute the right divisor. Oversampling rate should be 13 (as you know there is a JIRA to make over sampling factor more smartly in UART_open)

I will work with the internal clock tree owner to provide instruction to change the module clock to 192 MHz and provide clear instructions to update board library.

Regards,

Rahul

0 Rahul Prabhu over 7 years ago in reply to Rahul Prabhu

TI__Guru** 116170 points

Andreas,

I have been able to test changing the UART module clock to 192 Mhz on the AM572x using the UART3 instance that runs at 115.2 Kbps without issues. Here is the complete description of the changes.

The UART module clock selection of 48 Mhz or 192 Mhz is controlled by a register in the PRCM module using a register called CM_L4PER_UART3_CLKCTRL. In order to set 192 MHz clocking, the CM_L4PER_UART3_CLKCTRL[24] needs to be set to 1. Refer to the register description in the TRM.

To update this in the board library, add the following code to the idkAM572x_clock.c above the UART module clock enable. Refer file attached

	CSL_FINST(l4PerCmReg->CM_L4PER_UART3_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_CLKSEL, SEL_FUNC_192M_CLK);

Fullscreen idkAM572x_clock.c Download

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#include "board_internal.h"

/* Set the desired DDR3 configuration -- assumes 66.67 MHz DDR3 clock input */
Board_STATUS Board_moduleClockInit()
{
    CSL_cam_cm_coreRegs *camCmReg =
        (CSL_cam_cm_coreRegs *) CSL_MPU_CAM_CM_CORE_REGS;
    CSL_l4per_cm_core_componentRegs *l4PerCmReg =
        (CSL_l4per_cm_core_componentRegs *) CSL_MPU_L4PER_CM_CORE_REGS;
    CSL_l3init_cm_coreRegs *l3InitCmReg =
        (CSL_l3init_cm_coreRegs *) CSL_MPU_L3INIT_CM_CORE_REGS;
    CSL_core_cm_coreRegs *coreCmReg =
        (CSL_core_cm_coreRegs *) CSL_MPU_CORE_CM_CORE_REGS;
    CSL_coreaon_cm_coreRegs *coreAonCmReg =
        (CSL_coreaon_cm_coreRegs *) CSL_MPU_COREAON_CM_CORE_REGS;
    CSL_dss_cm_coreRegs *dssCmReg =
        (CSL_dss_cm_coreRegs *) CSL_MPU_DSS_CM_CORE_REGS;
    CSL_ipu_cm_core_aonRegs *ipuCmReg =
        (CSL_ipu_cm_core_aonRegs *) CSL_MPU_IPU_CM_CORE_AON_REGS;
    CSL_rtc_cm_core_aonRegs *rtcCmReg =
        (CSL_rtc_cm_core_aonRegs *) CSL_MPU_RTC_CM_CORE_AON_REGS;
    CSL_vpe_cm_core_aonRegs *vpeCmReg =
        (CSL_vpe_cm_core_aonRegs *) CSL_MPU_VPE_CM_CORE_AON_REGS;
    CSL_wkupaon_cmRegs *wkupAonCmReg =
        (CSL_wkupaon_cmRegs *) CSL_MPU_WKUPAON_CM_REGS;
    CSL_mpu_cm_core_aonRegs *mpuCmReg =
        (CSL_mpu_cm_core_aonRegs *) CSL_MPU_MPU_CM_CORE_AON_REGS;
    CSL_dsp1_cm_core_aonRegs *dsp1CmReg =
        (CSL_dsp1_cm_core_aonRegs *) CSL_MPU_DSP1_CM_CORE_AON_REGS;
    CSL_dsp2_cm_core_aonRegs *dsp2CmReg =
        (CSL_dsp2_cm_core_aonRegs *) CSL_MPU_DSP2_CM_CORE_AON_REGS;
    CSL_dsp1_prmRegs *dsp1PrmReg =
        (CSL_dsp1_prmRegs *) CSL_MPU_DSP1_PRM_REGS;
    CSL_dsp2_prmRegs *dsp2PrmReg =
        (CSL_dsp2_prmRegs *) CSL_MPU_DSP2_PRM_REGS;
    CSL_iva_cm_coreRegs *ivaCmReg =
        (CSL_iva_cm_coreRegs *) CSL_MPU_IVA_CM_CORE_REGS;

    /* PRCM clock domain state setting functions */
    CSL_FINST(camCmReg->CM_CAM_CLKSTCTRL_REG,
        CAM_CM_CORE_CM_CAM_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
/*
    while(CSL_CAM_CM_CORE_CM_CAM_CLKSTCTRL_REG_CLKACTIVITY_VIP1_GCLK_ACT !=
       CSL_FEXT(camCmReg->CM_CAM_CLKSTCTRL_REG,
        CAM_CM_CORE_CM_CAM_CLKSTCTRL_REG_CLKACTIVITY_VIP1_GCLK));
*/

    CSL_FINST(l4PerCmReg->CM_L4PER_CLKSTCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_CLKSTCTRL_REG_CLKACTIVITY_L4PER_L3_GICLK_ACT !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_CLKSTCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_CLKSTCTRL_REG_CLKACTIVITY_L4PER_L3_GICLK));

    CSL_FINST(l4PerCmReg->CM_L4PER2_CLKSTCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
/*
    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKACTIVITY_ICSS_CLK_ACT !=
       CSL_FEXT(l4PerCmReg->CM_L4PER2_CLKSTCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKACTIVITY_ICSS_CLK));
*/

    CSL_FINST(l4PerCmReg->CM_L4PER3_CLKSTCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER3_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER3_CLKSTCTRL_REG_CLKACTIVITY_L4PER3_L3_GICLK_ACT !=
       CSL_FEXT(l4PerCmReg->CM_L4PER3_CLKSTCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER3_CLKSTCTRL_REG_CLKACTIVITY_L4PER3_L3_GICLK));

    CSL_FINST(l3InitCmReg->CM_L3INIT_CLKSTCTRL_REG,
        L3INIT_CM_CORE_CM_L3INIT_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);

    while(CSL_L3INIT_CM_CORE_CM_L3INIT_CLKSTCTRL_REG_CLKACTIVITY_L3INIT_L3_GICLK_ACT !=
       CSL_FEXT(l3InitCmReg->CM_L3INIT_CLKSTCTRL_REG,
        L3INIT_CM_CORE_CM_L3INIT_CLKSTCTRL_REG_CLKACTIVITY_L3INIT_L3_GICLK));

    CSL_FINST(l3InitCmReg->CM_GMAC_CLKSTCTRL_REG,
        L3INIT_CM_CORE_CM_GMAC_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
/*
    while(CSL_L3INIT_CM_CORE_CM_GMAC_CLKSTCTRL_REG_CLKACTIVITY_GMII_250MHZ_CLK_ACT !=
       CSL_FEXT(l3InitCmReg->CM_GMAC_CLKSTCTRL_REG,
        L3INIT_CM_CORE_CM_GMAC_CLKSTCTRL_REG_CLKACTIVITY_GMII_250MHZ_CLK));
*/

    CSL_FINST(coreCmReg->CM_EMIF_CLKSTCTRL_REG,
        CORE_CM_CORE_CM_EMIF_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);

    while(CSL_CORE_CM_CORE_CM_EMIF_CLKSTCTRL_REG_CLKACTIVITY_EMIF_L3_GICLK_ACT !=
       CSL_FEXT(coreCmReg->CM_EMIF_CLKSTCTRL_REG,
        CORE_CM_CORE_CM_EMIF_CLKSTCTRL_REG_CLKACTIVITY_EMIF_L3_GICLK));

    CSL_FINST(coreCmReg->CM_L4CFG_CLKSTCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_CLKSTCTRL_REG_CLKTRCTRL, RESERVED_2);

    while(CSL_CORE_CM_CORE_CM_L4CFG_CLKSTCTRL_REG_CLKACTIVITY_L4CFG_L4_GICLK_ACT !=
       CSL_FEXT(coreCmReg->CM_L4CFG_CLKSTCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_CLKSTCTRL_REG_CLKACTIVITY_L4CFG_L4_GICLK));

    CSL_FINST(coreCmReg->CM_DMA_CLKSTCTRL_REG,
        CORE_CM_CORE_CM_DMA_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);

    while(CSL_CORE_CM_CORE_CM_DMA_CLKSTCTRL_REG_CLKACTIVITY_DMA_L3_GICLK_ACT !=
       CSL_FEXT(coreCmReg->CM_DMA_CLKSTCTRL_REG,
        CORE_CM_CORE_CM_DMA_CLKSTCTRL_REG_CLKACTIVITY_DMA_L3_GICLK));

    CSL_FINST(coreCmReg->CM_L3MAIN1_CLKSTCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_CLKSTCTRL_REG_CLKTRCTRL, RESERVED_2);

    while(CSL_CORE_CM_CORE_CM_L3MAIN1_CLKSTCTRL_REG_CLKACTIVITY_L3MAIN1_L3_GICLK_ACT !=
       CSL_FEXT(coreCmReg->CM_L3MAIN1_CLKSTCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_CLKSTCTRL_REG_CLKACTIVITY_L3MAIN1_L3_GICLK));

    CSL_FINST(coreCmReg->CM_IPU2_CLKSTCTRL_REG,
        CORE_CM_CORE_CM_IPU2_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
/*
    while(CSL_CORE_CM_CORE_CM_IPU2_CLKSTCTRL_REG_CLKACTIVITY_IPU2_GFCLK_ACT !=
       CSL_FEXT(coreCmReg->CM_IPU2_CLKSTCTRL_REG,
        CORE_CM_CORE_CM_IPU2_CLKSTCTRL_REG_CLKACTIVITY_IPU2_GFCLK));
*/

    CSL_FINST(coreAonCmReg->CM_COREAON_CLKSTCTRL_REG,
        COREAON_CM_CORE_CM_COREAON_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
/*
    while(CSL_COREAON_CM_CORE_CM_COREAON_CLKSTCTRL_REG_CLKACTIVITY_COREAON_L4_GICLK_ACT !=
       CSL_FEXT(coreAonCmReg->CM_COREAON_CLKSTCTRL_REG,
        COREAON_CM_CORE_CM_COREAON_CLKSTCTRL_REG_CLKACTIVITY_COREAON_L4_GICLK));
*/

    CSL_FINST(dssCmReg->CM_DSS_CLKSTCTRL_REG,
        DSS_CM_CORE_CM_DSS_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
/*
    while(CSL_DSS_CM_CORE_CM_DSS_CLKSTCTRL_REG_CLKACTIVITY_DSS_L3_GICLK_ACT !=
       CSL_FEXT(dssCmReg->CM_DSS_CLKSTCTRL_REG,
        DSS_CM_CORE_CM_DSS_CLKSTCTRL_REG_CLKACTIVITY_DSS_L3_GICLK));
*/

    CSL_FINST(ipuCmReg->CM_IPU1_CLKSTCTRL_REG,
        IPU_CM_CORE_AON_CM_IPU1_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
/*
    while(CSL_IPU_CM_CORE_AON_CM_IPU1_CLKSTCTRL_REG_CLKACTIVITY_IPU1_GFCLK_ACT !=
       CSL_FEXT(ipuCmReg->CM_IPU1_CLKSTCTRL_REG,
        IPU_CM_CORE_AON_CM_IPU1_CLKSTCTRL_REG_CLKACTIVITY_IPU1_GFCLK));
*/

    CSL_FINST(ipuCmReg->CM_IPU_CLKSTCTRL_REG,
        IPU_CM_CORE_AON_CM_IPU_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
/*
    while(CSL_IPU_CM_CORE_AON_CM_IPU_CLKSTCTRL_REG_CLKACTIVITY_IPU_L3_GICLK_ACT !=
       CSL_FEXT(ipuCmReg->CM_IPU_CLKSTCTRL_REG,
        IPU_CM_CORE_AON_CM_IPU_CLKSTCTRL_REG_CLKACTIVITY_IPU_L3_GICLK));
*/

    CSL_FINST(rtcCmReg->CM_RTC_CLKSTCTRL_REG,
        RTC_CM_CORE_AON_CM_RTC_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
/*
    while(CSL_RTC_CM_CORE_AON_CM_RTC_CLKSTCTRL_REG_CLKACTIVITY_RTC_L4_GICLK_ACT !=
       CSL_FEXT(rtcCmReg->CM_RTC_CLKSTCTRL_REG,
        RTC_CM_CORE_AON_CM_RTC_CLKSTCTRL_REG_CLKACTIVITY_RTC_L4_GICLK));
*/

    CSL_FINST(vpeCmReg->CM_VPE_CLKSTCTRL_REG,
        VPE_CM_CORE_AON_CM_VPE_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
/*
    while(CSL_VPE_CM_CORE_AON_CM_VPE_CLKSTCTRL_REG_CLKACTIVITY_VPE_GCLK_ACT !=
       CSL_FEXT(vpeCmReg->CM_VPE_CLKSTCTRL_REG,
        VPE_CM_CORE_AON_CM_VPE_CLKSTCTRL_REG_CLKACTIVITY_VPE_GCLK));
*/

    CSL_FINST(wkupAonCmReg->CM_WKUPAON_CLKSTCTRL_REG,
        WKUPAON_CM_CM_WKUPAON_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
/*
    while(CSL_WKUPAON_CM_CM_WKUPAON_CLKSTCTRL_REG_CLKACTIVITY_SYS_CLK_ACT !=
       CSL_FEXT(wkupAonCmReg->CM_WKUPAON_CLKSTCTRL_REG,
        WKUPAON_CM_CM_WKUPAON_CLKSTCTRL_REG_CLKACTIVITY_SYS_CLK));
*/

    CSL_FINST(mpuCmReg->CM_MPU_CLKSTCTRL_REG,
        MPU_CM_CORE_AON_CM_MPU_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
/*
    while(CSL_MPU_CM_CORE_AON_CM_MPU_CLKSTCTRL_REG_CLKACTIVITY_MPU_GCLK_ACT !=
       CSL_FEXT(mpuCmReg->CM_MPU_CLKSTCTRL_REG,
        MPU_CM_CORE_AON_CM_MPU_CLKSTCTRL_REG_CLKACTIVITY_MPU_GCLK));
*/

    /* Errata i872: ensure the DSP is powered-up and clocked for a brief time
     before enabling the DDR-related clocks below. Follow the sequence provided in errata i872.
     Start a SW force wakeup for DSPSS. */
    CSL_FINST(dsp1CmReg->CM_DSP1_CLKSTCTRL_REG,
        DSP1_CM_CORE_AON_CM_DSP1_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);

    // Enable DSPSS clock.
    CSL_FINST(dsp1CmReg->CM_DSP1_DSP1_CLKCTRL_REG,
        DSP1_CM_CORE_AON_CM_DSP1_DSP1_CLKCTRL_REG_MODULEMODE, AUTO);

    // Reset de-assertion for DSP SS logic.
    CSL_FINST(dsp1PrmReg->RM_DSP1_RSTCTRL_REG,
        DSP1_PRM_RM_DSP1_RSTCTRL_REG_RST_DSP1, CLEAR);

    // Wait until the module is functional.
    while(CSL_DSP1_CM_CORE_AON_CM_DSP1_DSP1_CLKCTRL_REG_IDLEST_FUNC != 
        CSL_FEXT(dsp1CmReg->CM_DSP1_DSP1_CLKCTRL_REG,
         DSP1_CM_CORE_AON_CM_DSP1_DSP1_CLKCTRL_REG_IDLEST));

/*
    while(CSL_DSP1_CM_CORE_AON_CM_DSP1_CLKSTCTRL_REG_CLKACTIVITY_DSP1_GFCLK_ACT !=
       CSL_FEXT(dsp1CmReg->CM_DSP1_CLKSTCTRL_REG,
        DSP1_CM_CORE_AON_CM_DSP1_CLKSTCTRL_REG_CLKACTIVITY_DSP1_GFCLK));
*/

    CSL_FINST(dsp2CmReg->CM_DSP2_CLKSTCTRL_REG,
        DSP2_CM_CORE_AON_CM_DSP2_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);

    // Enable DSPSS clock.
    CSL_FINST(dsp2CmReg->CM_DSP2_DSP2_CLKCTRL_REG,
        DSP2_CM_CORE_AON_CM_DSP2_DSP2_CLKCTRL_REG_MODULEMODE, AUTO);

    // Reset de-assertion for DSP SS logic.
    CSL_FINST(dsp2PrmReg->RM_DSP2_RSTCTRL_REG,
        DSP2_PRM_RM_DSP2_RSTCTRL_REG_RST_DSP2, CLEAR);

    // Wait until the module is functional.
    while(CSL_DSP2_CM_CORE_AON_CM_DSP2_DSP2_CLKCTRL_REG_IDLEST_FUNC != 
        CSL_FEXT(dsp2CmReg->CM_DSP2_DSP2_CLKCTRL_REG,
         DSP2_CM_CORE_AON_CM_DSP2_DSP2_CLKCTRL_REG_IDLEST));

/*
    while(CSL_DSP2_CM_CORE_AON_CM_DSP2_CLKSTCTRL_REG_CLKACTIVITY_DSP2_GFCLK_ACT !=
       CSL_FEXT(dsp2CmReg->CM_DSP2_CLKSTCTRL_REG,
        DSP2_CM_CORE_AON_CM_DSP2_CLKSTCTRL_REG_CLKACTIVITY_DSP2_GFCLK));
*/

    CSL_FINST(ivaCmReg->CM_IVA_CLKSTCTRL_REG,
        IVA_CM_CORE_CM_IVA_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
/*
    while(CSL_IVA_CM_CORE_CM_IVA_CLKSTCTRL_REG_CLKACTIVITY_IVA_GCLK_ACT !=
       CSL_FEXT(ivaCmReg->CM_IVA_CLKSTCTRL_REG,
        IVA_CM_CORE_CM_IVA_CLKSTCTRL_REG_CLKACTIVITY_IVA_GCLK));
*/

    /* PRCM Generic module mode setting functions */

    CSL_FINST(camCmReg->CM_CAM_VIP1_CLKCTRL_REG,
        CAM_CM_CORE_CM_CAM_VIP1_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CAM_CM_CORE_CM_CAM_VIP1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(camCmReg->CM_CAM_VIP1_CLKCTRL_REG,
        CAM_CM_CORE_CM_CAM_VIP1_CLKCTRL_REG_IDLEST));

    CSL_FINST(camCmReg->CM_CAM_VIP2_CLKCTRL_REG,
        CAM_CM_CORE_CM_CAM_VIP2_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CAM_CM_CORE_CM_CAM_VIP2_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(camCmReg->CM_CAM_VIP2_CLKCTRL_REG,
        CAM_CM_CORE_CM_CAM_VIP2_CLKCTRL_REG_IDLEST));

    CSL_FINST(camCmReg->CM_CAM_VIP3_CLKCTRL_REG,
        CAM_CM_CORE_CM_CAM_VIP3_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CAM_CM_CORE_CM_CAM_VIP3_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(camCmReg->CM_CAM_VIP3_CLKCTRL_REG,
        CAM_CM_CORE_CM_CAM_VIP3_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_DMA_DMA_SYSTEM_CLKCTRL_REG,
        CORE_CM_CORE_CM_DMA_DMA_SYSTEM_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_DMA_DMA_SYSTEM_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_DMA_DMA_SYSTEM_CLKCTRL_REG,
        CORE_CM_CORE_CM_DMA_DMA_SYSTEM_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_EMIF_DMM_CLKCTRL_REG,
        CORE_CM_CORE_CM_EMIF_DMM_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_EMIF_DMM_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_EMIF_DMM_CLKCTRL_REG,
        CORE_CM_CORE_CM_EMIF_DMM_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_EMIF_EMIF1_CLKCTRL_REG,
        CORE_CM_CORE_CM_EMIF_EMIF1_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_EMIF_EMIF1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_EMIF_EMIF1_CLKCTRL_REG,
        CORE_CM_CORE_CM_EMIF_EMIF1_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_EMIF_EMIF2_CLKCTRL_REG,
        CORE_CM_CORE_CM_EMIF_EMIF2_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_EMIF_EMIF2_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_EMIF_EMIF2_CLKCTRL_REG,
        CORE_CM_CORE_CM_EMIF_EMIF2_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_EMIF_EMIF_OCP_FW_CLKCTRL_REG,
        CORE_CM_CORE_CM_EMIF_EMIF_OCP_FW_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_EMIF_EMIF_OCP_FW_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_EMIF_EMIF_OCP_FW_CLKCTRL_REG,
        CORE_CM_CORE_CM_EMIF_EMIF_OCP_FW_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L3INSTR_L3_MAIN_2_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3INSTR_L3_MAIN_2_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L3INSTR_L3_MAIN_2_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L3INSTR_L3_MAIN_2_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3INSTR_L3_MAIN_2_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L3MAIN1_GPMC_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_GPMC_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L3MAIN1_GPMC_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L3MAIN1_GPMC_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_GPMC_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L3MAIN1_L3_MAIN_1_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L3MAIN1_L3_MAIN_1_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L3MAIN1_MMU_EDMA_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_MMU_EDMA_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L3MAIN1_MMU_EDMA_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L3MAIN1_MMU_EDMA_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_MMU_EDMA_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L3MAIN1_MMU_PCIESS_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_MMU_PCIESS_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L3MAIN1_MMU_PCIESS_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L3MAIN1_MMU_PCIESS_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_MMU_PCIESS_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L3MAIN1_OCMC_RAM1_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L3MAIN1_OCMC_RAM1_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L3MAIN1_OCMC_RAM2_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L3MAIN1_OCMC_RAM2_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L3MAIN1_OCMC_RAM3_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L3MAIN1_OCMC_RAM3_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L3MAIN1_OCMC_ROM_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_OCMC_ROM_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L3MAIN1_OCMC_ROM_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L3MAIN1_OCMC_ROM_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_OCMC_ROM_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L3MAIN1_TPCC_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_TPCC_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L3MAIN1_TPCC_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L3MAIN1_TPCC_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_TPCC_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L3MAIN1_TPTC1_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_TPTC1_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L3MAIN1_TPTC1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L3MAIN1_TPTC1_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_TPTC1_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L3MAIN1_TPTC2_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_TPTC2_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L3MAIN1_TPTC2_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L3MAIN1_TPTC2_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_TPTC2_CLKCTRL_REG_IDLEST));

// TODO: Check if enabled or AUTO
    CSL_FINS(coreCmReg->CM_L3MAIN1_VCP1_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_VCP1_CLKCTRL_REG_MODULEMODE, 2U);

    while(CSL_CORE_CM_CORE_CM_L3MAIN1_VCP1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L3MAIN1_VCP1_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_VCP1_CLKCTRL_REG_IDLEST));

    CSL_FINS(coreCmReg->CM_L3MAIN1_VCP2_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_VCP2_CLKCTRL_REG_MODULEMODE, 2U);

    while(CSL_CORE_CM_CORE_CM_L3MAIN1_VCP2_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L3MAIN1_VCP2_CLKCTRL_REG,
        CORE_CM_CORE_CM_L3MAIN1_VCP2_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L4CFG_L4_CFG_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_L4_CFG_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L4CFG_L4_CFG_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L4CFG_L4_CFG_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_L4_CFG_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX1_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX1_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX1_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX1_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX10_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX1_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX10_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX1_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX11_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX11_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX11_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX11_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX11_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX12_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX12_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX12_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX12_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX12_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX13_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX13_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX13_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX13_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX13_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX2_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX2_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX2_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX2_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX2_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX3_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX3_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX3_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX3_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX3_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX4_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX4_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX4_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX4_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX4_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX5_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX5_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX5_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX5_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX5_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX6_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX6_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX6_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX6_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX6_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX7_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX7_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX7_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX7_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX7_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX8_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX8_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX8_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX8_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX8_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX9_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX9_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX9_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX9_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_MAILBOX9_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_L4CFG_SPINLOCK_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_SPINLOCK_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_L4CFG_SPINLOCK_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(coreCmReg->CM_L4CFG_SPINLOCK_CLKCTRL_REG,
        CORE_CM_CORE_CM_L4CFG_SPINLOCK_CLKCTRL_REG_IDLEST));

    CSL_FINST(ipuCmReg->CM_IPU_TIMER5_CLKCTRL_REG,
        IPU_CM_CORE_AON_CM_IPU_TIMER5_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_IPU_CM_CORE_AON_CM_IPU_TIMER5_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(ipuCmReg->CM_IPU_TIMER5_CLKCTRL_REG,
        IPU_CM_CORE_AON_CM_IPU_TIMER5_CLKCTRL_REG_IDLEST));

    CSL_FINST(ipuCmReg->CM_IPU_TIMER6_CLKCTRL_REG,
        IPU_CM_CORE_AON_CM_IPU_TIMER6_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_IPU_CM_CORE_AON_CM_IPU_TIMER6_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(ipuCmReg->CM_IPU_TIMER6_CLKCTRL_REG,
        IPU_CM_CORE_AON_CM_IPU_TIMER6_CLKCTRL_REG_IDLEST));

    CSL_FINST(ipuCmReg->CM_IPU_TIMER7_CLKCTRL_REG,
        IPU_CM_CORE_AON_CM_IPU_TIMER7_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_IPU_CM_CORE_AON_CM_IPU_TIMER7_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(ipuCmReg->CM_IPU_TIMER7_CLKCTRL_REG,
        IPU_CM_CORE_AON_CM_IPU_TIMER7_CLKCTRL_REG_IDLEST));

    CSL_FINST(ipuCmReg->CM_IPU_TIMER8_CLKCTRL_REG,
        IPU_CM_CORE_AON_CM_IPU_TIMER8_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_IPU_CM_CORE_AON_CM_IPU_TIMER8_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(ipuCmReg->CM_IPU_TIMER8_CLKCTRL_REG,
        IPU_CM_CORE_AON_CM_IPU_TIMER8_CLKCTRL_REG_IDLEST));

    CSL_FINST(l3InitCmReg->CM_L3INIT_MMC1_CLKCTRL_REG,
        L3INIT_CM_CORE_CM_L3INIT_MMC1_CLKCTRL_REG_MODULEMODE, ENABLED);

    while(CSL_L3INIT_CM_CORE_CM_L3INIT_MMC1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l3InitCmReg->CM_L3INIT_MMC1_CLKCTRL_REG,
        L3INIT_CM_CORE_CM_L3INIT_MMC1_CLKCTRL_REG_IDLEST));

    CSL_FINST(l3InitCmReg->CM_L3INIT_MMC2_CLKCTRL_REG,
        L3INIT_CM_CORE_CM_L3INIT_MMC2_CLKCTRL_REG_MODULEMODE, ENABLED);

    while(CSL_L3INIT_CM_CORE_CM_L3INIT_MMC2_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l3InitCmReg->CM_L3INIT_MMC2_CLKCTRL_REG,
        L3INIT_CM_CORE_CM_L3INIT_MMC2_CLKCTRL_REG_IDLEST));

    CSL_FINST(l3InitCmReg->CM_GMAC_GMAC_CLKCTRL_REG,
        L3INIT_CM_CORE_CM_GMAC_GMAC_CLKCTRL_REG_MODULEMODE, ENABLED);

    while(CSL_L3INIT_CM_CORE_CM_GMAC_GMAC_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l3InitCmReg->CM_GMAC_GMAC_CLKCTRL_REG,
        L3INIT_CM_CORE_CM_GMAC_GMAC_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER2_L4_PER2_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_L4_PER2_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_L4_PER2_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER2_L4_PER2_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_L4_PER2_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER3_L4_PER3_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER3_L4_PER3_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER3_L4_PER3_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER3_L4_PER3_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER3_L4_PER3_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_GPIO2_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO2_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO2_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO2_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO2_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_GPIO3_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO3_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO3_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO3_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO3_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_GPIO4_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO4_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO4_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO4_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO4_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_GPIO5_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO5_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO5_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO5_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO5_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_GPIO6_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO6_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO6_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO6_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO6_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_GPIO7_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO7_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO7_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO7_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO7_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_GPIO8_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO8_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO8_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO8_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO8_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_I2C1_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C1_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_I2C1_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C1_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_I2C2_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C2_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C2_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_I2C2_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C2_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_I2C3_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C3_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C3_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_I2C3_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C3_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_I2C4_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C4_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C4_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_I2C4_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C4_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_L4_PER1_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_L4_PER1_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_L4_PER1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_L4_PER1_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_L4_PER1_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_MCSPI1_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI1_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_MCSPI1_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI1_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_MMC3_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_MMC3_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_MMC3_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_MMC3_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_MMC3_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_MMC4_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_MMC4_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_MMC4_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_MMC4_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_MMC4_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_TIMER10_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER10_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER10_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_TIMER10_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER10_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_TIMER11_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER11_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER11_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_TIMER11_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER11_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_TIMER2_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER11_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER11_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_TIMER2_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER11_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_TIMER3_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER3_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER3_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_TIMER3_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER3_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_TIMER4_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER4_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER4_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_TIMER4_CLKCTRL_REG,
        RTC_CM_CORE_AON_CM_RTC_RTCSS_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER_TIMER9_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER4_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER4_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_TIMER9_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER4_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER2_QSPI_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_QSPI_CLKCTRL_REG_MODULEMODE, ENABLED);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_QSPI_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER2_QSPI_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_QSPI_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER2_QSPI_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_QSPI_CLKCTRL_REG_CLKSEL_DIV, DIV4);

    CSL_FINST(l4PerCmReg->CM_L4PER2_QSPI_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_QSPI_CLKCTRL_REG_CLKSEL_SOURCE, SEL_PER_QSPI_CLK);

    CSL_FINST(l4PerCmReg->CM_L4PER_UART1_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_UART1_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_UART1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_UART1_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_UART1_CLKCTRL_REG_IDLEST));
		
	CSL_FINST(l4PerCmReg->CM_L4PER_UART3_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_CLKSEL, SEL_FUNC_192M_CLK);

    CSL_FINST(l4PerCmReg->CM_L4PER_UART3_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_UART3_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_IDLEST));
	
	CSL_FINST(l4PerCmReg->CM_L4PER_UART5_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_UART5_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_UART5_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_UART5_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_UART5_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER2_UART9_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART9_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART9_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER2_UART9_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART9_CLKCTRL_REG_IDLEST));

    CSL_FINS(mpuCmReg->CM_MPU_MPU_CLKCTRL_REG,
        MPU_CM_CORE_AON_CM_MPU_MPU_CLKCTRL_REG_MODULEMODE, 2U);

    while(CSL_MPU_CM_CORE_AON_CM_MPU_MPU_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(mpuCmReg->CM_MPU_MPU_CLKCTRL_REG,
        MPU_CM_CORE_AON_CM_MPU_MPU_CLKCTRL_REG_IDLEST));

    CSL_FINST(vpeCmReg->CM_VPE_VPE_CLKCTRL_REG,
        VPE_CM_CORE_AON_CM_VPE_VPE_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_VPE_CM_CORE_AON_CM_VPE_VPE_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(vpeCmReg->CM_VPE_VPE_CLKCTRL_REG,
        VPE_CM_CORE_AON_CM_VPE_VPE_CLKCTRL_REG_IDLEST));

    CSL_FINST(wkupAonCmReg->CM_WKUPAON_GPIO1_CLKCTRL_REG,
        WKUPAON_CM_CM_WKUPAON_GPIO1_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_WKUPAON_CM_CM_WKUPAON_GPIO1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(wkupAonCmReg->CM_WKUPAON_GPIO1_CLKCTRL_REG,
        WKUPAON_CM_CM_WKUPAON_GPIO1_CLKCTRL_REG_IDLEST));

    CSL_FINST(wkupAonCmReg->CM_WKUPAON_TIMER1_CLKCTRL_REG,
        WKUPAON_CM_CM_WKUPAON_TIMER1_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_WKUPAON_CM_CM_WKUPAON_TIMER1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(wkupAonCmReg->CM_WKUPAON_TIMER1_CLKCTRL_REG,
        WKUPAON_CM_CM_WKUPAON_TIMER1_CLKCTRL_REG_IDLEST));

    CSL_FINS(wkupAonCmReg->CM_WKUPAON_TIMER12_CLKCTRL_REG,
        WKUPAON_CM_CM_WKUPAON_TIMER12_CLKCTRL_REG_MODULEMODE, 2U);

    while(CSL_WKUPAON_CM_CM_WKUPAON_TIMER12_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(wkupAonCmReg->CM_WKUPAON_TIMER12_CLKCTRL_REG,
        WKUPAON_CM_CM_WKUPAON_TIMER12_CLKCTRL_REG_IDLEST));

    CSL_FINS(wkupAonCmReg->CM_WKUPAON_WD_TIMER1_CLKCTRL_REG,
        WKUPAON_CM_CM_WKUPAON_WD_TIMER1_CLKCTRL_REG_MODULEMODE, 2U);

    while(CSL_WKUPAON_CM_CM_WKUPAON_WD_TIMER1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(wkupAonCmReg->CM_WKUPAON_WD_TIMER1_CLKCTRL_REG,
        WKUPAON_CM_CM_WKUPAON_WD_TIMER1_CLKCTRL_REG_IDLEST));

    CSL_FINST(wkupAonCmReg->CM_WKUPAON_WD_TIMER2_CLKCTRL_REG,
        WKUPAON_CM_CM_WKUPAON_WD_TIMER2_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_WKUPAON_CM_CM_WKUPAON_WD_TIMER2_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(wkupAonCmReg->CM_WKUPAON_WD_TIMER2_CLKCTRL_REG,
        WKUPAON_CM_CM_WKUPAON_WD_TIMER2_CLKCTRL_REG_IDLEST));

    /* PRCM Specialized module mode setting functions */
    CSL_FINST(ivaCmReg->CM_IVA_SL2_CLKCTRL_REG,
        IVA_CM_CORE_CM_IVA_SL2_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_IVA_CM_CORE_CM_IVA_SL2_CLKCTRL_REG_IDLEST_DISABLE ==
       CSL_FEXT(ivaCmReg->CM_IVA_SL2_CLKCTRL_REG,
        IVA_CM_CORE_CM_IVA_SL2_CLKCTRL_REG_IDLEST));

    CSL_FINST(ivaCmReg->CM_IVA_IVA_CLKCTRL_REG,
        IVA_CM_CORE_CM_IVA_IVA_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_IVA_CM_CORE_CM_IVA_IVA_CLKCTRL_REG_IDLEST_DISABLE ==
       CSL_FEXT(ivaCmReg->CM_IVA_IVA_CLKCTRL_REG,
        IVA_CM_CORE_CM_IVA_IVA_CLKCTRL_REG_IDLEST));

    CSL_FINST(coreCmReg->CM_IPU2_IPU2_CLKCTRL_REG,
        CORE_CM_CORE_CM_IPU2_IPU2_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CORE_CM_CORE_CM_IPU2_IPU2_CLKCTRL_REG_IDLEST_DISABLE ==
       CSL_FEXT(coreCmReg->CM_IPU2_IPU2_CLKCTRL_REG,
        CORE_CM_CORE_CM_IPU2_IPU2_CLKCTRL_REG_IDLEST));

    CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,
        DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_MODULEMODE, ENABLED);
/*
    while(CSL_DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,
        DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_IDLEST));
*/

    CSL_FINST(ipuCmReg->CM_IPU1_IPU1_CLKCTRL_REG,
        IPU_CM_CORE_AON_CM_IPU1_IPU1_CLKCTRL_REG_MODULEMODE, AUTO);
/*
    while(CSL_IPU_CM_CORE_AON_CM_IPU1_IPU1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(ipuCmReg->CM_IPU1_IPU1_CLKCTRL_REG,
        IPU_CM_CORE_AON_CM_IPU1_IPU1_CLKCTRL_REG_IDLEST));
*/
    l4PerCmReg->CM_L4PER_GPIO2_CLKCTRL_REG |= (
        (CM_L4PER_GPIO2_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO2_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
        (CM_L4PER_GPIO2_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO2_CLKCTRL_MODULEMODE_SHIFT));

    l4PerCmReg->CM_L4PER_GPIO3_CLKCTRL_REG |= (
        (CM_L4PER_GPIO3_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO3_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
        (CM_L4PER_GPIO3_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO3_CLKCTRL_MODULEMODE_SHIFT));

    l4PerCmReg->CM_L4PER_GPIO4_CLKCTRL_REG |= (
        (CM_L4PER_GPIO4_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO4_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
        (CM_L4PER_GPIO4_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO4_CLKCTRL_MODULEMODE_SHIFT));

    l4PerCmReg->CM_L4PER_GPIO5_CLKCTRL_REG |= (
        (CM_L4PER_GPIO5_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO5_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
        (CM_L4PER_GPIO5_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO5_CLKCTRL_MODULEMODE_SHIFT));

    l4PerCmReg->CM_L4PER_GPIO6_CLKCTRL_REG |= (
        (CM_L4PER_GPIO6_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO6_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
        (CM_L4PER_GPIO6_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO6_CLKCTRL_MODULEMODE_SHIFT));

    l4PerCmReg->CM_L4PER_GPIO7_CLKCTRL_REG |= (
        (CM_L4PER_GPIO7_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO7_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
        (CM_L4PER_GPIO7_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO7_CLKCTRL_MODULEMODE_SHIFT));

    l4PerCmReg->CM_L4PER_GPIO8_CLKCTRL_REG |= (
        (CM_L4PER_GPIO8_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO8_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
        (CM_L4PER_GPIO8_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO8_CLKCTRL_MODULEMODE_SHIFT));

    CSL_FINST(l4PerCmReg->CM_L4PER_MCSPI2_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI2_CLKCTRL_REG_MODULEMODE, ENABLE);

    CSL_FINST(l4PerCmReg->CM_L4PER_MCSPI3_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI3_CLKCTRL_REG_MODULEMODE, ENABLE);

    CSL_FINST(l4PerCmReg->CM_L4PER2_PRUSS1_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS1_CLKCTRL_REG_MODULEMODE, DISABLED);

    CSL_FINST(l4PerCmReg->CM_L4PER2_PRUSS1_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS1_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_L4_PER2_CLKCTRL_REG_IDLEST_FUNC !=
        CSL_FEXT(l4PerCmReg->CM_L4PER2_PRUSS1_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS1_CLKCTRL_REG_IDLEST));

    CSL_FINST(l4PerCmReg->CM_L4PER2_PRUSS2_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS2_CLKCTRL_REG_MODULEMODE, DISABLED);

    CSL_FINST(l4PerCmReg->CM_L4PER2_PRUSS2_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS2_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_L4_PER2_CLKCTRL_REG_IDLEST_FUNC !=
        CSL_FEXT(l4PerCmReg->CM_L4PER2_PRUSS2_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS2_CLKCTRL_REG_IDLEST));

    while (CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKACTIVITY_ICSS_CLK_ACT !=
        CSL_FEXT(l4PerCmReg->CM_L4PER2_CLKSTCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKACTIVITY_ICSS_CLK));

    while (CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKACTIVITY_ICSS_IEP_CLK_ACT !=
        CSL_FEXT(l4PerCmReg->CM_L4PER2_CLKSTCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKACTIVITY_ICSS_IEP_CLK));

    while (CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKACTIVITY_PER_192M_GFCLK_ACT !=
        CSL_FEXT(l4PerCmReg->CM_L4PER2_CLKSTCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKACTIVITY_PER_192M_GFCLK));

    return BOARD_SOK;
}

Rebuild the board library using the following instructions: (Assuming build environment is setup)

cd pdk_am57xx_1_x_x\packages

gmake board_lib LIMIT_BOARDS=idkAM572x LIMIT_CORES=a15_0

After build completes, go to pdk_am57xx_1_x_xx\packages\ti\board\lib\idkAM572x\a15\release to confirm library was rebuilt.

Now, you are ready to build the application. In the application, make sure the board library is being used for enabling module clocks:

 Board_initCfg boardCfg;
    boardCfg = BOARD_INIT_PINMUX_CONFIG | 
            BOARD_INIT_MODULE_CLOCK |
        BOARD_INIT_UART_STDIO;
    Board_init(boardCfg);

If UART_soc.c file is not part of your project, add the file into the project and update the module clock for the UART instance that you are using. In this case, I have updated the module clock for UART3 as follows:

Fullscreen 0804.UART_soc.c Download

/**
 * @file   UART_soc.c
 *
 * @brief  This file defines the UART interface structure specific to AM57x
 */
/*
 * Copyright (c) 2014 - 2016, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
/** ============================================================================*/

#include <ti/csl/csl_utils.h>
#include <ti/csl/soc/am572x/src/cslr_soc.h>
#include <ti/drv/uart/UART.h>
#include <ti/drv/uart/soc/UART_soc.h>
#ifdef UART_DMA_ENABLE
#include <ti/sdo/edma3/drv/edma3_drv.h>
#endif

/* UART configuration structure */
UART_HwAttrs uartInitCfg[CSL_UART_PER_CNT] =
{ {
#ifdef _TMS320C6X
        CSL_DSP_UART1_REGS,
        OSAL_REGINT_INTVEC_EVENT_COMBINER, /* Use an interrupt vector # other than one used by EDMA */
#elif defined(__ARM_ARCH_7A__)
        CSL_MPU_UART1_REGS,
        104,
#else
        CSL_IPU_UART1_REGS,
        24,
#endif
        34,  /* used only for C6x, reserved DSP1_IRQ_34 */
        CSL_UART_0_MODULE_FREQ,
        CSL_EDMA3_CHA_UART0_RX,
        CSL_EDMA3_CHA_UART0_TX,
        0,
        0,
        0,
        0,
        0,
        NULL,
        UART_RXTRIGLVL_8,
        UART_TXTRIGLVL_56,
        TRUE, /* default DMA mode */
        FALSE, /* Loopback disabled by default */
		TRUE, /* Interrupt enabled by default */
    },
    {
#ifdef _TMS320C6X
        CSL_DSP_UART2_REGS,
        OSAL_REGINT_INTVEC_EVENT_COMBINER,
#elif defined(__ARM_ARCH_7A__)
        CSL_MPU_UART2_REGS,
        105,
#else
        CSL_IPU_UART2_REGS,
        24,
#endif
        34,  /* used only for C6x, reserved DSP1_IRQ_34 */
        CSL_UART_1_MODULE_FREQ,
        CSL_EDMA3_CHA_UART1_RX,
        CSL_EDMA3_CHA_UART1_TX,
        0,
        0,
        0,
        0,
        0,
        NULL,
        UART_RXTRIGLVL_8,
        UART_TXTRIGLVL_56,
        TRUE, /* default DMA mode */
        FALSE, /* Loopback disabled by default */
		TRUE, /* Interrupt enabled by default */
    },
    {
#ifdef _TMS320C6X
        CSL_DSP_UART3_REGS,
        OSAL_REGINT_INTVEC_EVENT_COMBINER,
#elif defined(__ARM_ARCH_7A__)
        CSL_MPU_UART3_REGS,
        106,
#else
        CSL_IPU_UART3_REGS,
        45,
#endif
        34,  /* used only for C6x, reserved DSP1_IRQ_34 */
        192000000,
        CSL_EDMA3_CHA_UART2_RX,
        CSL_EDMA3_CHA_UART2_TX,
        0,
        0,
        0,
        0,
        0,
        NULL,
        UART_RXTRIGLVL_8,
        UART_TXTRIGLVL_56,
        TRUE, /* default DMA mode */
        FALSE, /* Loopback disabled by default */
		TRUE, /* Interrupt enabled by default */
    },
    {
#ifdef _TMS320C6X
        CSL_DSP_UART4_REGS,
        OSAL_REGINT_INTVEC_EVENT_COMBINER,
#elif defined(__ARM_ARCH_7A__)
        CSL_MPU_UART4_REGS,
        102,
#else
        CSL_IPU_UART4_REGS,
        24,
#endif
        34,  /* used only for C6x, reserved DSP1_IRQ_34 */
        CSL_UART_3_MODULE_FREQ,
        CSL_EDMA3_CHA_UART3_RX,
        CSL_EDMA3_CHA_UART3_TX,
        0,
        0,
        0,
        0,
        0,
        NULL,
        UART_RXTRIGLVL_8,
        UART_TXTRIGLVL_56,
        TRUE, /* default DMA mode */
        FALSE, /* Loopback disabled by default */
		TRUE, /* Interrupt enabled by default */
    },
    {
#ifdef _TMS320C6X
        CSL_DSP_UART5_REGS,
        OSAL_REGINT_INTVEC_EVENT_COMBINER,
#elif defined(__ARM_ARCH_7A__)
        CSL_MPU_UART5_REGS,
        137,
#else
        CSL_IPU_UART5_REGS,
        24,
#endif
        34,  /* used only for C6x, reserved DSP1_IRQ_34 */
        CSL_UART_4_MODULE_FREQ,
        CSL_EDMA3_CHA_UART4_RX,
        CSL_EDMA3_CHA_UART4_TX,
        0,
        0,
        0,
        0,
        0,
        NULL,
        UART_RXTRIGLVL_8,
        UART_TXTRIGLVL_56,
        TRUE, /* default DMA mode */
        FALSE, /* Loopback disabled by default */
		TRUE, /* Interrupt enabled by default */
    },
    {
#ifdef _TMS320C6X
        CSL_DSP_UART6_REGS,
        OSAL_REGINT_INTVEC_EVENT_COMBINER,
#elif defined(__ARM_ARCH_7A__)
        CSL_MPU_UART6_REGS,
        138,
#else
        CSL_IPU_UART6_REGS,
        24,
#endif
        34,  /* used only for C6x, reserved DSP1_IRQ_34 */
        CSL_UART_5_MODULE_FREQ,
        CSL_EDMA3_CHA_UART5_RX,
        CSL_EDMA3_CHA_UART5_TX,
        0,
        0,
        0,
        0,
        0,
        NULL,
        UART_RXTRIGLVL_8,
        UART_TXTRIGLVL_56,
        TRUE, /* default DMA mode */
        FALSE, /* Loopback disabled by default */
		TRUE, /* Interrupt enabled by default */
    },
    {
#ifdef _TMS320C6X
        CSL_DSP_UART7_REGS,
        OSAL_REGINT_INTVEC_EVENT_COMBINER,
#elif defined(__ARM_ARCH_7A__)
        CSL_MPU_UART7_REGS,
        104,
#else
        CSL_IPU_UART7_REGS,
        24,
#endif
        34,  /* used only for C6x, reserved DSP1_IRQ_34 */
        CSL_UART_6_MODULE_FREQ,
        CSL_EDMA3_CHA_UART6_RX,
        CSL_EDMA3_CHA_UART6_TX,
        0,
        0,
        0,
        0,
        0,
        NULL,
        UART_RXTRIGLVL_8,
        UART_TXTRIGLVL_56,
        TRUE, /* default DMA mode */
        FALSE, /* Loopback disabled by default */
		TRUE, /* Interrupt enabled by default */
    },
    {
#ifdef _TMS320C6X
        CSL_DSP_UART8_REGS,
        OSAL_REGINT_INTVEC_EVENT_COMBINER,
#elif defined(__ARM_ARCH_7A__)
        CSL_MPU_UART8_REGS,
        104,
#else
        CSL_IPU_UART8_REGS,
        24,
#endif
        CSL_INTC_EVENTID_UARTINT7,
        CSL_UART_7_MODULE_FREQ,
        CSL_EDMA3_CHA_UART7_RX,
        CSL_EDMA3_CHA_UART7_TX,
        0,
        0,
        0,
        0,
        0,
        NULL,
        UART_RXTRIGLVL_8,
        UART_TXTRIGLVL_56,
        TRUE, /* default DMA mode */
        FALSE, /* Loopback disabled by default */
		TRUE, /* Interrupt enabled by default */
    },
    {
#ifdef _TMS320C6X
        CSL_DSP_UART9_REGS,
        OSAL_REGINT_INTVEC_EVENT_COMBINER,
#elif defined(__ARM_ARCH_7A__)
        CSL_MPU_UART9_REGS,
        104,
#else
        CSL_IPU_UART9_REGS,
        24,
#endif
        34,  /* used only for C6x, reserved DSP1_IRQ_34 */
        CSL_UART_8_MODULE_FREQ,
        CSL_EDMA3_CHA_UART8_RX,
        CSL_EDMA3_CHA_UART8_TX,
        0,
        0,
        0,
        0,
        0,
        NULL,
        UART_RXTRIGLVL_8,
        UART_TXTRIGLVL_56,
        TRUE, /* default DMA mode */
        FALSE, /* Loopback disabled by default */
		TRUE, /* Interrupt enabled by default */
    },
    {
#ifdef _TMS320C6X
        CSL_DSP_UART10_REGS,
        OSAL_REGINT_INTVEC_EVENT_COMBINER,
#elif defined(__ARM_ARCH_7A__)
        CSL_MPU_UART10_REGS,
        104,
#else
        CSL_IPU_UART10_REGS,
        24,
#endif
        34,  /* used only for C6x, reserved DSP1_IRQ_34 */
        CSL_UART_9_MODULE_FREQ,
        CSL_EDMA3_CHA_UART9_RX,
        CSL_EDMA3_CHA_UART9_TX,
        0,
        0,
        0,
        0,
        0,
        NULL,
        UART_RXTRIGLVL_8,
        UART_TXTRIGLVL_56,
        TRUE, /* default DMA mode */
        FALSE, /* Loopback disabled by default */
		TRUE, /* Interrupt enabled by default */
    },
};

/* UART objects */
UART_V1_Object UartObjects[CSL_UART_PER_CNT];

/* UART configuration structure */
CSL_PUBLIC_CONST UART_Config UART_config[CSL_UART_PER_CNT + 1U] = {
    {
        &UART_FxnTable_v1,
        &UartObjects[0],
        &uartInitCfg[0]
    },

    {
        &UART_FxnTable_v1,
        &UartObjects[1],
        &uartInitCfg[1]
    },

    {
        &UART_FxnTable_v1,
        &UartObjects[2],
        &uartInitCfg[2]
    },

    {
        &UART_FxnTable_v1,
        &UartObjects[3],
        &uartInitCfg[3]
    },

    {
        &UART_FxnTable_v1,
        &UartObjects[4],
        &uartInitCfg[4]
    },

    {
        &UART_FxnTable_v1,
        &UartObjects[5],
        &uartInitCfg[5]
    },
    {
        &UART_FxnTable_v1,
        &UartObjects[6],
        &uartInitCfg[6]
    },

    {
        &UART_FxnTable_v1,
        &UartObjects[7],
        &uartInitCfg[7]
    },

    {
        &UART_FxnTable_v1,
        &UartObjects[8],
        &uartInitCfg[8]
    },
    {
        &UART_FxnTable_v1,
        &UartObjects[9],
        &uartInitCfg[9]
    },
    {NULL, NULL, NULL}
};

/**
 * \brief  This API gets the SoC level of UART intial configuration
 *
 * \param  index     UART instance index.
 * \param  cfg       Pointer to UART SOC initial config.
 *
 * \return 0 success: -1: error
 *
 */
int32_t UART_socGetInitCfg(uint32_t index, UART_HwAttrs *cfg)
{
    int32_t ret = 0;

    if (index < CSL_UART_PER_CNT)
    {
        *cfg = uartInitCfg[index];
    }
    else
    {
        ret = (-((int32_t)1));
    }

    return ret;
}

/**
 * \brief  This API sets the SoC level of UART intial configuration
 *
 * \param  index     UART instance index.
 * \param  cfg       Pointer to UART SOC initial config.
 *
 * \return           0 success: -1: error
 *
 */
int32_t UART_socSetInitCfg(uint32_t index, const UART_HwAttrs *cfg)
{
    int32_t ret = 0;

    if (index < CSL_UART_PER_CNT)
    {
        uartInitCfg[index] = *cfg;
    }
    else
    {
        ret = (-((int32_t)1));
    }

    return ret;
}

Then rebuild your application and run the UART application. I used UART_BasicExample_idkAM572x_armExampleProject as my test case where I confirmed the test still runs at 115.2 kbps when the module clock is updated to 192 Mhz.

Please note the files and the steps shared are for UART3 instance for the idkAM572x, you will need to change the steps accordingly for the instance of UART that you are using.

Let us know if you have any questions regarding this setup.

Regards,

Rahul

0 Andreas Halbe over 7 years ago in reply to Rahul Prabhu

Intellectual 455 points

Hello Rahul,

Thank you for the quick response. I think I did exactly what you described, just for the UART 5 instance we are using on the EvaBoard (since this instance is accessible on the J21 connector).

Inside mian() I do the follwoing:

UART_socGetInitCfg(4, &uart_cfg); // Use instance 4, which is UART 5. We made the changes inside the board lib specifically for this UART instance!
uart_cfg.frequency = 192000000; // Indicate that the UART module input frequency is 192,000,000[Hz] after we changed the board libbrary
UART_socSetInitCfg(4, &uart_cfg); // Use instance 4, which is UART 5. We made the changes inside the board lib specifically for this UART instance!

if (Board_initUART() == false)
{
System_printf("\nBoard_initUART failed!\n");
return(0);
}

Afterwards I run my application specific function:

Here is some code lines just before sending one character:

/* This is debug code and needs to be removed */
pHwAttrs = (UART_HwAttrs *)uart->hwAttrs; // Point to the HW attributes of my UART handle

u32_Temp = uartParams.baudRate; // Shows in the debugger 2,500,000 // Means UART handle has been opened with the desired baud-rate
u32_Temp = pHwAttrs->frequency; // Shows in the debugger: 192,000,000, means UART_soc.c is modified
u32_Temp = *(uint32_t *)0x4A009870; // CM_L4PER_UART5_CLKCTRL shows in the debugger: 16,777,218 = 0x0100,0002, means 192[MHz] is selected for UART 5

UARTFIFOCharPut(pHwAttrs->baseAddr, 'O'); // Now I send a single ASCII 'O' via the CSL

I will attach a picture of my logic analyzer, which shows me that a character 'O' is being send but with the baud-rate of 3[Mbps]. Please check the start bit, which has the length of 0.33[us], but the desired bit-length is 0.4[us] for a 2.5[Mbps] baud-rate.

Can you please check on your side, if you are able to transmit with 2.5[Mbps] when selecting this baud-rate inside the "uartParams" structure?

Thanks,

Andreas

0 Rahul Prabhu over 7 years ago in reply to Andreas Halbe

TI__Guru** 116170 points

Andreas,

Could you please indicate what over sampling rate are you using 16x or 13x ? Can you also indicate what value do you read from the UART_DLL and UART_DLH.

I suspect that he issue here is with the incorrect setting of the UART divisor. Let me explain.

Oversampling factor of 16

When you are trying to compute the divisor to get ot 2.5 Mhz, the compute goes as follows:

Divisor = 192000000/ (16*2500000) = 4.8 but in the UARTDivisorValCompute does an integer divide and round it to 4

So resulting baud rate is

Actual baud rate = 192000000/ (16*4) = 3 Mbps

If it was rounded to 5, the baudrate would be 192000000/(16*5) = 2.4 Mbps.

Oversampling factor of 13

When you are trying to compute the divisor to get ot 2.5 Mhz, the compute goes as follows:

Divisor = 192000000/ (13*2500000) = 5.9 but in the UARTDivisorValCompute does an integer divide and round it to 5

So resulting baud rate is

Actual baud rate = 192000000/ (13*5) = 2.953 Mbps

If it was rounded to 6, the baud rate would be 192000000/(13*6) =2.461538

How to fix the issue

In the longer term setting the divisor to closest integer should be the final fix for this issue which we are tracking as part of the bug we have filed to set the divisor and oversampling more smartly in the UART_open.

In the near term can you try a quick workaround. You can set the uartParams.baudRate = 24000000. this will set the divisors to 5 (for oversampling of 16 ) and to 6 (for oversampling of 13). this should get you within 5 % error and resolve the problem.

Regards,

Rahul

0 Andreas Halbe over 7 years ago in reply to Rahul Prabhu

Intellectual 455 points

Hello Rahul,

maybe you remember that we already has to set the oversampling factor to 13 due to the problem that we could not achieve a baud-rate of 921,600[bps]. I am referring to the following post:

e2e.ti.com/.../2571837

I read 3 additional registers (DLL and DLH are not logical to me since I expect a divisor of 6. Am I reading the wrong registers?):

u32_Temp = *(uint32_t *)0x48066000; // UART 5 DLL register shows in the debugger: 0x4F
u32_Temp = *(uint32_t *)0x48066004; // UART 5 DLH register shows in the debugger: 0x05
u32_Temp = *(uint32_t *)0x48066020; // UART 5 MDR1 register shows in the debugger: 0x03

However, if I select as a baud-rate uartParams.baudrate = 2,400,000 (according to you suggestion above), then the values inside the above 3 registers do not change but the baud-rate of 2.5[Mbps] is correct in the logic analyzer. That means that I achieve the expected baud-rate, but please let me know why I see those values inside the debugger.

Thanks a lot so far for your support,

Andreas

0 Rahul Prabhu over 7 years ago in reply to Andreas Halbe

TI__Guru** 116170 points

Andreas,

There is some inbuilt protection mechanism that is available for configuration registers so that rogue code doesn`t change the functionality during normal operation. This is referred to as configuration mode where the configurations latch the writes and in normal mode writes are ignored. To read the divisor value, you need to setup DIV_EN field in the UART5_LCR register.

Refer to the description of LCR register and Table 24-140 for registers that are accessible in normal mode and configuration mode. Also, refer to latched access in the UART module.

Regards,
Rahul

PS: I performed a quick experiment by opening memory browser after running the Board_init code and modified the LCR register for UART3 from 0x3 to 0x83 and was able to read back the divisor correctly as 104 (0x68) for 192 MHz module clock when setting up 115.2 kbps. I am trying to understand from the design team why they mask the divisor value during normal operation.

0 Rahul Prabhu over 7 years ago in reply to Rahul Prabhu

TI__Guru** 116170 points

Andreas,

Was this issue resolved. Are you able to read the DLL And DLH correctly after setting up DIV_EN in UART5_LCR?

Regards,
Rahul

0 Rahul Prabhu over 7 years ago in reply to Rahul Prabhu

TI__Guru** 116170 points

Andreas,

I wanted to provide an quick update on this. The development team has accepted the issue regarding configuration of oversampling parameter and the issue with rounding the UART divisor to the closest integer value and will be addressing these issues in PRSDK 5.1 release in 3Q2018.

the also intend to provide an API in UART_soc.c file that will allow users to switch from 48 Mhz to 192 MHz without having to do this in the board library but the application user will need to call the API and then update the UART module clock in the HWAttr before calling UART_open for the baud rate to be set correctly.

you can use the following bug IDs to track the changed in release notes:

PRSDK-4187: Option to switch UART module clock from 48 Mhz to 192 Mhz
PRSDK-4197: UARTDivisorValCompute not rounding the divisor to closest integer
PRSDK-4105: Option to configure oversampling factor between 13x and 16x

Since we are following up on other UART RTS signalling requirement on a separate thread can you please close this since you have the UART working at the right baud rate now.

Regards,
Rahul

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RTOS/AM5728: 2.5Mbps UART baudrate