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CCS/AM5716: IPU Unicache configuration

hungwei yang
Expert 1090 points

Part Number: AM5716
Other Parts Discussed in Thread: SYSBIOS

Tool/software: Code Composer Studio

Hello,

I m trying to use UNICACHE to speed up my program. However, it seems the UNICACHE doesn't work, because I measure the execution time by SCTM and the time doesn't decrease.

I found out the CACHE_CONFIG[1]BYPASS is not set which means everything is non-cachable, so I tried but failed to set the BYPASS bit by modifying the gel file "ccs_base\emulation\boards\am571x\gel\AM571x_multicore_reset.gel". I have no idea what to do next, please give some comment and help.

BR,

Hungwei

  • 0
    TI__Guru**** 393215 points
    Hi,

    What software is this? TI-RTOS?
  • 0 in reply to Biser Gatchev-XID
    Expert 1090 points
    No. It a very simple program executing 256 NOP instructions which is written by me.
  • 0 in reply to hungwei yang
    TI__Mastermind 43296 points
    hungwei,

    Can you try to enable the unicache with sysbios config?

    /* Enable cache */
    var Cache = xdc.useModule('ti.sysbios.hal.unicache.Cache');
    Cache.enableCache = true;

    Regards,
    Garrett
  • 0 in reply to Garrett Ding
    Expert 1090 points

    Hello Garrett,

    I m not using sysbios and likely wont use it for our future projects. Can you recommend other ways to enable UNICACHE? Can I write IPU1_UNICACHE_CFG registers thorough ICE when the IPU1_UNICACHE reset is asserted?

    BR,
    Hungwei

  • 0 in reply to hungwei yang
    Expert 1090 points

    Hello,

    Is there any updates?

    Thanks,
    Hungwei

  • 0 in reply to hungwei yang
    TI__Mastermind 43296 points
    hungwei,

    Have you put IPU unicache out of reset? see Figure 7-5. IPUx Subsystem Reset Scheme. IPU1_RST in PRCM module is reset signal to the IPU1_UNICACHE and the IPU1_MMU.

    The reset deassertion for IPU Unicache/MMU in ccs_base\emulation\boards\am571x\gel\AM571x_multicore_reset.gel may help.

    Regards,
    Garrett
  • 0 in reply to Garrett Ding
    Expert 1090 points

    Hello Garrett,

    >Have you put IPU unicache out of reset?

    Yes. Actually I enable IPU1_0 by executing AM571x_multicore_reset.gel. After running the gel script, the values of RM_IPU1_RSTCTRL[2:0] and RM_IPU1_RSTST[2:0] are 0 which means the C0/C1/UNICACHE/MMU are all out of reset, right?

    Hungwei

  • 0 in reply to hungwei yang
    TI__Mastermind 43296 points
    Hungwei,

    That's correct - the values of RM_IPU1_RSTCTRL[2:0] and RM_IPU1_RSTST[2:0] are 0 which means the C0/C1/UNICACHE/MMU are all out of reset.
    Have you tried to manually modify the BYPASS bit from CCS - > View-> Registers-> IPU1_UNICACHE_CFG->CACHE_CONFIG->BYPASS (1-BYPASS_1) before running your application?

    Regards,
    Garrett
  • 0 in reply to Garrett Ding
    Expert 1090 points

    Hello Garrett,

    >Have you tried to manually modify the BYPASS bit from CCS - > View-> Registers-> IPU1_UNICACHE_CFG->CACHE_CONFIG->BYPASS (1-BYPASS_1) before running your application?

    No. I will give it a try and let u know the result later.

    I have manually modified the BYPASS bit from memory browser but it failed.

    Best Regards,
    Hungwei

  • 0 in reply to hungwei yang
    Expert 1090 points

    Hello Garrett,

    >Have you tried to manually modify the BYPASS bit from CCS - > View-> Registers-> IPU1_UNICACHE_CFG->CACHE_CONFIG->BYPASS (1-BYPASS_1) before running your application?

    It works! And the execution time decreases due to the effort of UNICACHE.

    I still have 2 questions for you

    1) 

    I see different values of UNICACHE_CFG between "memory browser view of CA15" and "register view of M4". Furthermore, I cannot modify the register value from memory browser of CA15. Is it reasonable?

    2)

    I measure the execution time of my test program with SCTM and find out it spends about 2000~2100 CPU cycles on executing 1024 NOP instructions. Is the time reasonable?

    I suppose the execution time should be about 1000~1100 CPU cycles, because the M4 TRM shows 1 NOP instruction costs 1 CPU cycles. And my test program should be run on cache which is a zero-wait memory device.

    Thanks for any comment.

    Regards,
    Hungwei

  • 0 in reply to hungwei yang
    TI__Mastermind 43296 points

    Hungwei,

    1) IPU unicache_cfg should be accessible from A15. This seems to be a CCS scripting issue. From the footnote of TRM Table 2-9. IPU Memory Map - (2) Can also be accessed from L3_MAIN (by other initiators, such as: MPU, DSP, etc).

    2) 2000 CPU cycles for 1024 NOP seems to be higher than expected as you noted for single cycle instruction in M4. We can continue to investigate in the new thread you created - e2e.ti.com/.../714585

    Regards,
    Garrett

  • 0 in reply to Garrett Ding
    Expert 1090 points

    Hello Garrett,

    (1) It is OK. I will use "register view" to modify the values of registers instead of "memory view".

    (2) OK.

    Thanks a lot.

    Regards,

    Hungwei