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RTOS/TMDXIDK5728: To be recognized by Windows PC as a PCIe device

Hideaki Nambu
Mastermind 9165 points
Part Number: TMDXIDK5728
Other Parts Discussed in Thread: AM5728

Tool/software: TI-RTOS


Hello,
My customer is trying to connect the titled EVM to a Windows PC.
Could you please advise a detailed procedure or a remaining steps for them ?

References:

A sample code:
C:\ti\pdk_am57xx_1_0_11\packages\ti\drv\pcie\example\sample\src

Doxigen:
C:\ti\pdk_am57xx_1_0_11\packages\ti\drv\pcie\docs\doxygen\html\index.html

PDF:
PCIe UG www.ti.com/.../sprugs6d.pdf

My customer found some procedures for linux SDK, but their OS shuold be TI-RTOS or baremetal.

Goal:

Windows finds the EVM and its device manager displays it like as unknown device or something.

H/W Connection:

- Windows PC as a root complex.
- TMDXIDK5728 as a end point.
- A LVDS cable to tie theie PCIe connectors.

Test result:

Fail.
The EVM logged a link training and link-up, but on the other hand, no icons in the windows device manager.

EVM log:

E
*                EP mode                     *
*                EP mode                     *
**********************************************

Version #: 0x0202000d; string PCIE LLD Revision: 02.02.00.13:Aug  7 2018:22:
17:55

PCIe Power Up.
PLL configured.
PowerUP linkCap gen=2 change to 1
Successfully configured Inbound Translation!
Successfully configured Outbound Translation!
Starting link training...
Link is up.
Checking link speed and # of lanes
Expect 1 lanes, found 1 lanes (PASS)
Expect gen 1 speed, found gen 1 speed (PASS)


....


Vendor ID = 0x**** //(edit)
Device ID = 0x**** //(edit)
Device Status = 0x100146
Class Code = 0x0
Class Revision = 0x1
Class + Rev = 0x1

 

 

 

  • 0
    TI__Guru* 95265 points
    Hi,

    "Test result:
    Fail.
    The EVM logged a link training and link-up, but on the other hand, no icons in the windows device manager."

    From the AM5728 IDK side, do you have CCS JTAG to check the LTSSM status is L0 and stable? See AM5728 TRM Table 24-1087. PCIECTRL_TI_CONF_DEVICE_CMD LTSSM_STATE field for more information.

    From your description, you didn't mention that you modify the AM5728 IDK hardware, also you didn't change the PCIE reference clock from the outside. It looks to me that you use the AM5728 IDK EVM HW/SW as it is and I don't expect that will work.

    So, the first thing, please clarify if you can monitor a stable LTSSM in L0 state on AM5728 side. Also, please clarify if you made any HW/SW modification on AM57298 side.

    Then, please check e2e.ti.com/.../653443 for discussion for required modification if you didn't do so.

    Regards, Eric
  • 0 in reply to lding
    Mastermind 9165 points

    lding
    Thank you for your response.


    The H/W modification has not been tried.

    Your link explains based on J6 EVM.

    I tried to translate it to the TMDXIDK5728.

    Can I ask some?

    Q. Could yo please review my translation?

    Q. R806 and R807 were not found in our IDK. No problem?

  • 0 in reply to Hideaki Nambu
    TI__Guru* 95265 points
    Hi,

    I asked our HW engineer to comment this.

    Regards, Eric
  • 0 in reply to lding
    TI__Mastermind 42545 points

    Hi,

    The instructions in the table are correct but there is a big difference between implementing this on the VAYU EVM vs the TMDXDK5728.

    The VAYU EVM has the capacitors adjacent allowing a zero ohm resistor to be installed to short the REF_CLK on the PCIe connector to the SoC as shown below.

    The TMDXIDK5728 was not designed in this way. Connecting these signals on the TMDXIDK5728 will require a pair of twisted wires connected between the PCIe connector side of C436 and C437 to the SoC side of C538 and C539 as shown below. The wire must connect the pad on C438 to the pad on C436 and the pad on C437 to the pad for C439. They cannot be reversed. The wires must be kept at the same length. 

    Regards, Bill

  • 0 in reply to Bill Taboada
    Mastermind 9165 points
    Bill,
    Thank you very much, espeially for your drawing.
    I will talk to my customer.