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AM5728: Register configuration about Sampling rate conversion

matusan
Guru 10235 points
Part Number: AM5728

Hello, TI Experts,

 

Our customer sent us questions about Sampling rate conversion with AM5728.

 

They found below description in TRM(SPRUHZ6J): "24.6.1 McASP Overview"

Two independent clock generator modules for transmit and receive.

     – Clocking flexibility allows the McASP to receive and transmit at different rates. For example, the

       McASP can receive data at 48 kHz but output up-sampled data at 96 kHz or 192 kHz.

 

So, They expect AM5728 has "Sampling rate conversion HW".

 

Question:

- Are there any "Sampling rate conversion HW" in AM5728?

- Could you tell us how to realize this below example exactly?

     "the McASP can receive data at 48 kHz but output up-sampled data at 96 kHz or 192 kHz"

   (Which registers should be configure?)

 

We would appreciate if you tell us the recommended way of "Sampling rate conversion" of McASP with AM5728 including related register configuration.

 

Best regards,

  • 0
    TI__Intellectual 2350 points

    Hi Matu-san,

    The case that you referred to in the McASP chapter of the TRM is just an example, meant to highlight its clocking flexibility (totally independent Rx/Tx clocking).  The point is that IF you're upsampling data (with your own SW), you are able to transmit it at that higher rate, even if the incoming data is at a lower sample rate.  AM5728 does not have a HW ASRC block.

    The only current device with a HW ASRC is the 66AK2G12, so please have a look if this is an important feature for you.  The K2G TRM has a chapter on the ASRC block.

    Good luck!

  • 0
    Guru 10235 points

    Part Number: AM5728

    Hello, TI Experts,

     

    Our customer sent us an question about how to realize Sampling rate conversion(SRC) with DSP on AM5728.

    They would like to realize like below operation.

    　- CPU(A15) sent the "44.1KHz wav file" data to the DSP(C66x).

        - McASP captures "192KHz I2S data" and send to the DSP(C66x).

        - The DSP SRC operation convert the CPU sending "44.1KHz wav file" data" to 192KHz.

        - The DSP also mixed the McASP sending "192KHz I2S data" to this SRC applied data.

        - The mixed data is transferred from the same McASP.

     

    Question:

      - McASP can capture "192KHz I2S data" properly without MCLK?

    Best regards,

  • 0
    TI__Guru**** 393215 points
    Please clarify which clock you refer by "MCLK"? This is usually a codec signal, and represents the main clock for the codec. A codec will not be functional without this signal. On the AM57x McASP side the required I2S clock signals for receive are MCASPx_FSR and MCASPx_ACLKR.
  • 0 in reply to Biser Gatchev-XID
    Guru 10235 points

    Hi,

    Thank you very much for your kindness.

    I really appreciate your help.

    I get the detail from the customer.

    They told us "MCLK" means such as "AUXCLK,AHCLKx,AHCLKR".

    We understand "I2S clock signals for receive are MCASPx_FSR and MCASPx_ACLKR" which you said.

    Question:

     - They would like to use McASP like attached pdf.

        Is it work properly?

    If you have any notice or comment, please tell us.

    Best regards,

    chart.pdf

  • 0 in reply to matusan
    TI__Intellectual 2350 points

    Hello again, Matu-san,

    From what I see in the PDF, your customer wants to run a McASP's Tx and Rx sections synchronously, with both clock zones being fed the same bit clock and frame sync - Rx and Tx are both slaves to the same clocks.  Is that right?

    To answer your question: It's OK not to use AHCLKs on McASP if you're providing all clocks to it externally.  McASP really only uses AHCLK signals in order to divide them down, if you wanted to generate bit clock and frame sync internally.  You're not trying to do that here, so it's OK not to connect it.  However, if you have access to the MCLK, you should still connect it to AHCLKX in case the customer wants to use the clock-check feature.

    I recommend that you set this up a little differently from your drawing.  Feed the BCLK and LRCLK to ACLKX and AFSX, not to ACLKR and AFSR.  Then go into the ACLKCTL register and set the ASYNC bit to 0.  This way the Rx side will internally use the Tx clocks as reference.  This has two advantages:

    -when ASYNC = 0, McASP will internally flip the polarity of the Rx clocks (with respect to the Tx clocks) such that you receive on one edge (let's say falling) and transmit on the other edge (rising).  This is usually the way that you want to do it, especially if you've got synchronous Rx and Tx. 

    -this way you can do a single route from the customer board's clock pin to the corresponding pin on the AM572x.  It's good to avoid "T" branching when you can, for signal integrity reasons.

    I hope this helps, let me know if you have more questions.

  • 0 in reply to Tufino
    Guru 10235 points
    Hello,

    Thank you very much for your detail explanation.
    This information is very helpful!
    I will send the answer to the customer.

    Best regards,