OMAPL138B-EP: questions on DRAM timing diagram & interfacing to OMAPL138

Hi Leo,

For all DDR interfaces the PHY sits between the controller and the IO’s talking to the DDR memory. The PHY uses clock to launch all signals to the DDR.
The DDR devices uses the clock to latch all command/address signals, and DQS to latch write DQ/DM. Similarly, the PHY uses DQS to latch read DQ.

For writes to the DDR memory, the valid data window is centered around the DQS edge.
For reads from the DDR memory, the valid data window is edge aligned with the DQS edge. The PHY has a DLL that is locked onto the DQS and performs a 90 degree phase shift on the DQS signal before using this recovered edge to latch the data.

Refer to the JESD79-2 DDR2 JEDEC Specification or one of many available appnotes online (search for something like "ddr memory dll dqs edge aligned centered"). The JEDEC specification provides tables and calculations for setup and hold time.

What problem are you specifically trying to solve? If its performing timing analysis for a DDR2 memory, we provide routing guidelines for robust DDR2 performance instead of providing signal timings. Refer to the DDR section of the datasheet. The DDR2 controller on the OMAP-L138 is compliant to the JEDEC specification, which conveys the timing and signal integrity requirements.

Regards,
Mark