66AK2G12: DSP and DDR3 are not working properly. When SD card is inserted, data transmission will be interrupted Is this problem caused by DQS?Please see the attachment for detailed explanation.

Hi,

This is not a software issue. The DQS signals are part of the data byte lane grouping described in Table 14 of the DDR3 Design Requirements for Keystone Devices (SPRABI1C).  The DQS0 must be connected to the appropriate DQS  pin on the memory device for the lower eight bits of the data bus.  The connection shown in the attached power point will strobe the wrong portion of the data bus for eight bit accesses.  Since 16bit accesses will strobe both DQS0 and DQS1 the memory interface is working. This is only true because the length of the DQS0 signal must be close to the length of the lower data bits and vice versa.  If the length was significantly different you would see access problems for both 8bit and 16bit access. 

There is no software work-around for this problem. You must modify your board to correct the faulty DQS routing.  Be sure the meet all the length matching requirements for the data byte lanes once the change has been made.

Regards, Bill