AM5718: Audio clock configuration

Hi

A gentle reminder

Regards
Satheesh Kumar S

Satheesh Kumar,

satheesh kumar32 said:

No clock at CLOCKOUT2 through DTS. 

satheesh kumar32 said:

With this device node

satheesh kumar32 said:

cannot update CM_COREAON_CLKOUTMUX2_CLKCTRL

From what I understand, your main issue is that you are not able to provide clock signal from AM571x clkout2 pin to AIC3106 MCLK pin.

satheesh kumar32 said:

McASP3 as Master and codec as slave(Both bit clock and frame sync)

But if your AM571x McASP3 is Master, then you might not need to provide clock to AIC3106 MCLK pin. You can check this with our audio experts in the Audio forum:

https://e2e.ti.com/support/audio/f/6

Check below e2e thread for example:

https://e2e.ti.com/support/audio/f/6/t/836146

https://e2e.ti.com/support/audio/f/6/t/193778

Explain our Audio experts that you will use AIC3106 codec in slave mode, explain what exactly you will do with this codec, and they will be able to confirm if MCLK is needed or not, for your usecase.

satheesh kumar32 said:

1) For integrating TLV320AIC3106 with AM5718 ,is there any kernel source modification is needed(davinci-evm.c,davinci-mcasp.c) as mentioned in the document.

No, davinci-evm.c and/or davinci-mcasp.c update is not needed (at least for CLKOUT2 generation).

satheesh kumar32 said:

2) SDK contain one defconfig file for all these board,porting instruction given in the SDK linux documentation will work without any kernel source modification.If any correction in my thought,pl z clarify. 

You can use the default tisdk_am57xx-evm_defconfig

satheesh kumar32 said:

2)with device tree,How can I configure McSAP as Master and codec as slave, and bit clock as 3.072MHz,Frame sync =48KHz.

You need to populate correct values for simple-audio-card,bitclock-master and simple-audio-card,frame-master. For example of McASP master, codec slave configuration, refer to below DTS files:

linux-kernel/arch/arm/boot/dts/dra72-evm-common.dtsi

Frame sync value is passed to audio tools (arecord/aplay) or to audio application, and bit clock is calculated by the driver.

Regards,
Pavel

Hi,

We are following the scheme provided in AM5728 GP for the codec design. Codec we use is AIC3106.

 I Guess this is equivalent to what is given in ""SLAA469"". www.ti.com/.../slaa469.pdf

In the above case MCLK,WCLK,BCLK are generated by Host Processor (AM57xx). I guess same process is followed in AM5728. We are also adopted the same scheme. 

So as understand McASP3 of AM57xx is in master mode offering BCLK and WCLK.

Regards

Satheesh

Satheesh,

In AM572x TI EVM, McASP is slave. In this EVM, FS and bit clock are generated by the AIC3x codec, thus MCLK must be provided.

linux-kernel/arch/arm/boot/am57xx-beagle-x15-common.dtsi

sound0: sound0 {
        compatible = "simple-audio-card";
        simple-audio-card,name = "BeagleBoard-X15";
        simple-audio-card,widgets =
            "Line", "Line Out",
            "Line", "Line In";
        simple-audio-card,routing =
            "Line Out",    "LLOUT",
            "Line Out",    "RLOUT",
            "MIC2L",    "Line In",
            "MIC2R",    "Line In";
        simple-audio-card,format = "dsp_b";
        simple-audio-card,bitclock-master = <&sound0_master>;
        simple-audio-card,frame-master = <&sound0_master>;
        simple-audio-card,bitclock-inversion;

        simple-audio-card,cpu {
            sound-dai = <&mcasp3>;
        };

        sound0_master: simple-audio-card,codec {
            sound-dai = <&tlv320aic3104>;
            clocks = <&clkout2_clk>;
        };
    };

You might be in the case discussed for "Figure 4. ASI Slave Mode (Generating Master Clock from BCLK)" , but you need to check and confirm this in Audio forum, where AIC3104 experts can suggest you.

Regards,
Pavel

Hi Pavel

Thanks for your support

ok,I understood

We will proceed this way

I have configured the kernel through menuconfig and modified the device tree as you mentioned above.

system clock frequency is 24.576MHz. I have plan to operate audio codec at 12.288MHz.

is it possible to divide 24.576MHz to 12.288MHz through device tree?.

I cannot update register(CM_COREAON_CLKOUTMUX2_CLKCTRL,CM_CLKSEL_SYS_CLK2_CLKOUTMUX(0x4AE0 61CC)) through device tree.

From our previous discussion it was done through register write in last.c file.

Is this register update possible with device tree?

If I include register write in last.c file,I guess audio codec initialisation may takes place before clockout2 (MCLK) signal? 

I have tried different combination still not working.

one more doubt

In mcASP3 node,op-mode = <0>; /* MCASP_IIS_MODE */ It is for I2S mode

But in sound node,it is put as   simple-audio-card,format = "dsp_b";

why this difference?

i am attaching the modified dts

/*
 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "am571x-idk-common.dtsi"

/ {
	model = "TI AM5718 IDK";

	aliases {
		ethernet4 = &pruss1_emac0;
		ethernet5 = &pruss1_emac1;
		sound0 = &sound0;
	};

	/* Dual mac ethernet application node on icss2 */
	pruss1_eth: pruss1_eth {
		status = "okay";
		compatible = "ti,am57-prueth";
		prus = <&pru1_0>, <&pru1_1>;
		firmware-name = "ti-pruss/am57xx-pru0-prueth-fw.elf",
				"ti-pruss/am57xx-pru1-prueth-fw.elf";
		ti,pruss-gp-mux-sel = <0>,	/* GP, default */
				      <4>;	/* MII2, needed for PRUSS1_MII1 */
		sram = <&ocmcram1>;
		interrupt-parent = <&pruss1_intc>;
		interrupts = <20>, <21>;
		interrupt-names = "rx_red_hp", "rx_red_lp";

		pruss1_emac0: ethernet-mii0 {
			phy-handle = <&pruss1_eth0_phy>;
			phy-mode = "mii";
			interrupts = <20>, <22>, <23>, <26>;
			interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
					  "emac_ptp_tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};

		pruss1_emac1: ethernet-mii1 {
			phy-handle = <&pruss1_eth1_phy>;
			phy-mode = "mii";
			interrupts = <21>, <23>, <24>, <27>;
			interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
					  "emac_ptp_tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};
	};
sound0: sound0 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "BeagleBoard-X15";
		simple-audio-card,widgets =
			"Line", "Line Out",
			"Line", "Line In";
		simple-audio-card,routing =
			"Line Out",	"LLOUT",
			"Line Out",	"RLOUT",
			"MIC2L",	"Line In",
			"MIC2R",	"Line In";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <&sound0_master>;
		simple-audio-card,frame-master = <&sound0_master>;
		simple-audio-card,bitclock-inversion;

		simple-audio-card,cpu {
			sound-dai = <&mcasp3>;
		};

		sound0_master: simple-audio-card,codec {
			sound-dai = <&tlv320aic3106>;
			clocks = <&clkout2_clk>;
		};
	};
};

&pruss1_mdio {
	status = "okay";
	reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
	pruss1_eth0_phy: ethernet-phy@0 {
		reg = <0>;
		interrupt-parent = <&gpio3>;
		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
	};

	pruss1_eth1_phy: ethernet-phy@1 {
		reg = <1>;
		interrupt-parent = <&gpio3>;
		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
	};
};

&pruss2_eth {
	ti,pruss-gp-mux-sel = <4>,	/* MII2, needed for PRUSS1_MII0 */
			      <4>;	/* MII2, needed for PRUSS1_MII1 */
};
&mcasp3 {
	#sound-dai-cells = <0>;
	assigned-clocks = <&mcasp3_ahclkx_mux>;
	assigned-clock-parents = <&sys_clkin2>;
	status = "okay";

	op-mode = <0>;	/* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializers */
	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

#include "am57xx-evm-cmem-am571x.dtsi"

/*
 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include "am57xx-industrial-grade.dtsi"

/ {
	aliases {
		rtc0 = &tps659038_rtc;
		rtc1 = &rtc;
		display0 = &hdmi0;
		ethernet2 = &pruss2_emac0;
		ethernet3 = &pruss2_emac1;
	};

	chosen {
		stdout-path = &uart3;
	};

	vmain: fixedregulator-vmain {
		compatible = "regulator-fixed";
		regulator-name = "VMAIN";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	v3_3d: fixedregulator-v3_3d {
		compatible = "regulator-fixed";
		regulator-name = "V3_3D";
		vin-supply = <&smps9_reg>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vtt_fixed: fixedregulator-vtt {
		/* TPS51200 */
		compatible = "regulator-fixed";
		regulator-name = "vtt_fixed";
		vin-supply = <&v3_3d>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
	};
	vdd_3v3: fixedregulator-vdd_3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vdd_3v3";
		vin-supply = <&regen1>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	aic_dvdd: fixedregulator-aic_dvdd {
		compatible = "regulator-fixed";
		regulator-name = "aic_dvdd_fixed";
		vin-supply = <&vdd_3v3>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	src_clk_x1: src_clk_x1 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <20000000>;
	};

	leds-iio {
		status = "disabled";
		compatible = "gpio-leds";
		led-out0 {
			label = "out0";
			gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out1 {
			label = "out1";
			gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out2 {
			label = "out2";
			gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out3 {
			label = "out3";
			gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out4 {
			label = "out4";
			gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out5 {
			label = "out5";
			gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out6 {
			label = "out6";
			gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out7 {
			label = "out7";
			gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	hdmi0: connector@0 {
		compatible = "hdmi-connector";
		label = "hdmi";

		type = "a";

		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&tpd12s015_out>;
			};
		};
	};

	tpd12s015: encoder@0 {
		compatible = "ti,tpd12s016", "ti,tpd12s015";

		gpios = <0>, /* optional CT_CP_HPD */
			<0>, /* optional LS_OE */
			<&gpio7 12 GPIO_ACTIVE_HIGH>;	/* HPD */

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				tpd12s015_in: endpoint@0 {
					remote-endpoint = <&hdmi_out>;
				};
			};

			port@1 {
				reg = <1>;

				tpd12s015_out: endpoint@0 {
					remote-endpoint = <&hdmi_connector_in>;
				};
			};
		};
	};

	src_clk_x1: src_clk_x1 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <20000000>;
	};

	/* Dual-MAC Ethernet application node on PRU-ICSS2 */
	pruss2_eth: pruss2_eth {
		compatible = "ti,am57-prueth";
		prus = <&pru2_0>, <&pru2_1>;
		firmware-name = "ti-pruss/am57xx-pru0-prueth-fw.elf",
				"ti-pruss/am57xx-pru1-prueth-fw.elf";
		sram = <&ocmcram1>;
		interrupt-parent = <&pruss2_intc>;
		interrupts = <20>, <21>;
		interrupt-names = "rx_red_hp", "rx_red_lp";

		pruss2_emac0: ethernet-mii0 {
			phy-handle = <&pruss2_eth0_phy>;
			phy-mode = "mii";
			interrupts = <20>, <22>, <23>, <26>;
			interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
					  "emac_ptp_tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};

		pruss2_emac1: ethernet-mii1 {
			phy-handle = <&pruss2_eth1_phy>;
			phy-mode = "mii";
			interrupts = <21>, <23>, <24>, <27>;
			interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
					  "emac_ptp_tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};
	};

	ptp_bc: ptp_bc {
		compatible = "ti,am57-bc";
		status = "disabled";
	};
};

&dra7_pmx_core {
	dcan1_pins_default: dcan1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* dcan1_tx */
			DRA7XX_CORE_IOPAD(0x37d4, PIN_INPUT_PULLUP | MUX_MODE0)		/* dcan1_rx */
		>;
	};

	dcan1_pins_sleep: dcan1_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
			DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP)	/* dcan1_rx.off */
		>;
	};
};

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;

	tps659038: tps659038@58 {
		compatible = "ti,tps659038";
		reg = <0x58>;
		interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_HIGH
			       &dra7_pmx_core 0x418>;
		#interrupt-cells = <2>;
		interrupt-controller;
		ti,system-power-controller;
		ti,palmas-override-powerhold;

		tps659038_pmic {
			compatible = "ti,tps659038-pmic";

			smps12-in-supply = <&vmain>;
			smps3-in-supply = <&vmain>;
			smps45-in-supply = <&vmain>;
			smps6-in-supply = <&vmain>;
			smps7-in-supply = <&vmain>;
			smps8-in-supply = <&vmain>;
			smps9-in-supply = <&vmain>;
			ldo1-in-supply = <&vmain>;
			ldo2-in-supply = <&vmain>;
			ldo3-in-supply = <&vmain>;
			ldo4-in-supply = <&vmain>;
			ldo9-in-supply = <&vmain>;
			ldoln-in-supply = <&vmain>;
			ldousb-in-supply = <&vmain>;
			ldortc-in-supply = <&vmain>;

			regulators {
				smps12_reg: smps12 {
					/* VDD_MPU */
					regulator-name = "smps12";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1250000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps3_reg: smps3 {
					/* VDD_DDR EMIF1 EMIF2 */
					regulator-name = "smps3";
					regulator-min-microvolt = <1350000>;
					regulator-max-microvolt = <1350000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps45_reg: smps45 {
					/* VDD_DSPEVE on AM572 */
					/* VDD_IVA + VDD_DSP on AM571 */
					regulator-name = "smps45";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1250000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps6_reg: smps6 {
					/* VDD_GPU */
					regulator-name = "smps6";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1250000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps7_reg: smps7 {
					/* VDD_CORE */
					regulator-name = "smps7";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1150000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps8_reg: smps8 {
					/* 5728 - VDD_IVAHD */
					/* 5718 - N.C. test point */
					regulator-name = "smps8";
				};

				smps9_reg: smps9 {
					/* VDD_3_3D */
					regulator-name = "smps9";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo1_reg: ldo1 {
					/* VDDSHV8 - VSDMMC  */
					/* NOTE: on rev 1.3a, data supply */
					regulator-name = "ldo1";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <3300000>;
					regulator-boot-on;
					regulator-always-on;
				};

				ldo2_reg: ldo2 {
					/* VDDSH18V */
					regulator-name = "ldo2";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo3_reg: ldo3 {
					/* R1.3a 572x V1_8PHY_LDO3: USB, SATA */
					regulator-name = "ldo3";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo4_reg: ldo4 {
					/* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
					regulator-name = "ldo4";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				/* LDO5-8 unused */

				ldo9_reg: ldo9 {
					/* VDD_RTC  */
					regulator-name = "ldo9";
					regulator-min-microvolt = <840000>;
					regulator-max-microvolt = <1160000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldoln_reg: ldoln {
					/* VDDA_1V8_PLL */
					regulator-name = "ldoln";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldousb_reg: ldousb {
					/* VDDA_3V_USB: VDDA_USBHS33 */
					regulator-name = "ldousb";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldortc_reg: ldortc {
					/* VDDA_RTC  */
					regulator-name = "ldortc";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				regen1: regen1 {
					/* VDD_3V3_ON */
					regulator-name = "regen1";
					regulator-boot-on;
					regulator-always-on;
				};

				regen2: regen2 {
					/* Needed for PMIC internal resource */
					regulator-name = "regen2";
					regulator-boot-on;
					regulator-always-on;
				};
			};
		};

		tps659038_rtc: tps659038_rtc {
			compatible = "ti,palmas-rtc";
			interrupt-parent = <&tps659038>;
			interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
			wakeup-source;
		};

		tps659038_pwr_button: tps659038_pwr_button {
			compatible = "ti,palmas-pwrbutton";
			interrupt-parent = <&tps659038>;
			interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
			wakeup-source;
			ti,palmas-long-press-seconds = <12>;
		};

		tps659038_gpio: tps659038_gpio {
			compatible = "ti,palmas-gpio";
			gpio-controller;
			#gpio-cells = <2>;
		};

		extcon_usb2: tps659038_usb {
			compatible = "ti,palmas-usb-vid";
			ti,enable-vbus-detection;
			ti,enable-id-detection;
			/* ID & VBUS GPIOs provided in board dts */
		};
	};

	tpic2810: tpic2810@60 {
		compatible = "ti,tpic2810";
		reg = <0x60>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	tc358778: tc358778@0e {
		compatible = "toshiba,tc358778", "toshiba,tc358768";
		reg = <0x0e>;
		status = "disabled";

		clocks = <&src_clk_x1>;
		clock-names = "refclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				tc358778_in: endpoint {
					remote-endpoint = <&dpi_out>;
					data-lines = <24>;
				};
			};

			port@1 {
				reg = <1>;
				tc358778_out: endpoint {
					/*
					 * lanes and remote-endpoint defined per
					 * panel.
					 */
				};
			};
		};
	};

	ov2659: ov2659@30 {
		compatible = "ovti,ov2659";
		reg = <0x30>;

		clocks = <&src_clk_x1>;
		clock-names = "xvclk";

		pwrdn-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;

		port {
			ov2659_1: endpoint {
				hsync-active = <1>;
				vsync-active = <1>;
				pclk-sample = <1>;
				link-frequencies = /bits/ 64 <70000000>;
			};
		};
	};

tlv320aic3106: tlv320aic3106@18 {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3106";
		reg = <0x18>;
		assigned-clocks = <&clkoutmux2_clk_mux>;
		assigned-clock-parents = <&sys_clk2_dclk_div>;

		status = "okay";
		adc-settle-ms = <40>;

		AVDD-supply = <&vdd_3v3>;
		IOVDD-supply = <&vdd_3v3>;
		DRVDD-supply = <&vdd_3v3>;
		DVDD-supply = <&aic_dvdd>;
	};
};

&mcspi3 {
	status = "okay";
	ti,pindir-d0-out-d1-in;

	sn65hvs882: sn65hvs882@0 {
		compatible = "pisosr-gpio";
		gpio-controller;
		#gpio-cells = <2>;

		reg = <0>;
		spi-max-frequency = <1000000>;
		spi-cpol;
	};
};

&uart3 {
	status = "okay";
	interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH
			       &dra7_pmx_core 0x248>;
};

&rtc {
	status = "okay";
	ext-clk-src;
};

&mac {
	status = "okay";
	dual_emac;
};

&cpsw_emac0 {
	phy_id = <&davinci_mdio>, <0>;
	phy-mode = "rgmii";
	dual_emac_res_vlan = <1>;
};

&cpsw_emac1 {
	phy_id = <&davinci_mdio>, <1>;
	phy-mode = "rgmii";
	dual_emac_res_vlan = <2>;
};

&usb2_phy1 {
	phy-supply = <&ldousb_reg>;
};

&usb2_phy2 {
	phy-supply = <&ldousb_reg>;
};

&usb1 {
	dr_mode = "host";
};

&omap_dwc3_2 {
	extcon = <&extcon_usb2>;
};

&usb2 {
	extcon = <&extcon_usb2>;
	dr_mode = "otg";
};

&mmc1 {
	status = "okay";
	vmmc-supply = <&v3_3d>;
	vqmmc-supply = <&ldo1_reg>;
	bus-width = <4>;
	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
};

&mmc2 {
	status = "okay";
	vmmc-supply = <&v3_3d>;
	vqmmc-supply = <&v3_3d>;
	bus-width = <8>;
	non-removable;
	max-frequency = <96000000>;
	no-1-8-v;
};

&dcan1 {
	status = "okay";
	pinctrl-names = "default", "sleep", "active";
	pinctrl-0 = <&dcan1_pins_sleep>;
	pinctrl-1 = <&dcan1_pins_sleep>;
	pinctrl-2 = <&dcan1_pins_default>;
};

&qspi {
	status = "okay";

	spi-max-frequency = <76800000>;
	m25p80@0 {
		compatible = "s25fl256s1", "jedec,spi-nor";
		spi-max-frequency = <76800000>;
		reg = <0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		#address-cells = <1>;
		#size-cells = <1>;

		/* MTD partition table.
		 * The ROM checks the first four physical blocks
		 * for a valid file to boot and the flash here is
		 * 64KiB block size.
		 */
		partition@0 {
			label = "QSPI.SPL";
			reg = <0x00000000 0x000040000>;
		};
		partition@1 {
			label = "QSPI.u-boot";
			reg = <0x00040000 0x00100000>;
		};
		partition@2 {
			label = "QSPI.u-boot-spl-os";
			reg = <0x00140000 0x00080000>;
		};
		partition@3 {
			label = "QSPI.u-boot-env";
			reg = <0x001c0000 0x00010000>;
		};
		partition@4 {
			label = "QSPI.u-boot-env.backup1";
			reg = <0x001d0000 0x0010000>;
		};
		partition@5 {
			label = "QSPI.kernel";
			reg = <0x001e0000 0x0800000>;
		};
		partition@6 {
			label = "QSPI.file-system";
			reg = <0x009e0000 0x01620000>;
		};
	};
};

&gpu {
	status = "ok";
};

&hdmi {
	status = "okay";
	/*
	 * XXX: Support AM572x-Rev 1.2a. this is wrong for AM571x-rev 1.3a,
	 * AM572x-Rev1.3a - but thanks to always-on, they work.
	 * TODO: SWITCH TO LDO4 once rev 1.2a is deprecated
	 * (on rev 1.3a availability)
	 */
	vdda-supply = <&ldo3_reg>;

	port {
		hdmi_out: endpoint {
			remote-endpoint = <&tpd12s015_in>;
		};
	};
};

&dss {
	status = "okay";

	vdda_video-supply = <&ldoln_reg>;

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;

			dpi_out: endpoint {
				remote-endpoint = <&tc358778_in>;
				data-lines = <24>;
			};
		};
	};
};

&bb2d {
	status = "okay";
};

&pruss_soc_bus1 {
	status = "okay";

	pruss1: pruss@0 {
		status = "okay";
	};
};

&pruss_soc_bus2 {
	status = "okay";

	pruss2: pruss@0 {
		status = "okay";
	};
};

&pruss2_mdio {
	status = "okay";
	pruss2_eth0_phy: ethernet-phy@0 {
		reg = <0>;
		interrupt-parent = <&gpio3>;
		interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
	};

	pruss2_eth1_phy: ethernet-phy@1 {
		reg = <1>;
		interrupt-parent = <&gpio3>;
		interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
	};
};

&cpu0 {
	vdd-supply = <&smps12_reg>;
};

i have added two extra node from beagle board

vdd_3v3: fixedregulator-vdd_3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
vin-supply = <&regen1>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};

aic_dvdd: fixedregulator-aic_dvdd {
compatible = "regulator-fixed";
regulator-name = "aic_dvdd_fixed";
vin-supply = <&vdd_3v3>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};

Regards

Satheesh Kumar S

Hi pavel

A gentle reminder 

Regards

Satheesh Kumar S

satheesh kumar32 said:

Satheesh Kumar

satheesh kumar32 said:

system clock frequency is 24.576MHz. I have plan to operate audio codec at 12.288MHz.

is it possible to divide 24.576MHz to 12.288MHz through device tree?.

I cannot update register(CM_COREAON_CLKOUTMUX2_CLKCTRL,CM_CLKSEL_SYS_CLK2_CLKOUTMUX(0x4AE0 61CC)) through device tree.

From our previous discussion it was done through register write in last.c file.

Is this register update possible with device tree?

If I include register write in last.c file,I guess audio codec initialisation may takes place before clockout2 (MCLK) signal? 

Again, I would suggest you to check in Audio forum if that AIC3104 MCLK is needed at all. If yes, then we can proceed searching a way to supply it through AM571x clkout2 pin.

You can also compare how AIC3104 operates with the changes from last.c (clkout2 enabled) and without these changes (clkout2 disabled). If you observe that AIC3104 does not work properly without MCLK, we can proceed searching a way to enable clkout2 in DTS (instead of last.c).

satheesh kumar32 said:

one more doubt

In mcASP3 node,op-mode = <0>; /* MCASP_IIS_MODE */ It is for I2S mode

But in sound node,it is put as   simple-audio-card,format = "dsp_b";

why this difference?

These are two different parameters. First is operating mode, second is format.

op-mode: I2S/DIT ops mode. 0 for I2S mode. 1 for DIT mode used for S/PDIF, IEC60958-1, and AES-3 formats. Usually only 0 (I2S) is used.

The McASP device driver differentiates two types of operation modes: I2S and DIT. I2S mode more generally refers to time division multiplexing(TDM) mode. Digital Audio Interface Transmission (DIT) mode is used for S/PDIF. The operational mode is configured through the following Device Tree (DT) parameters:
op-mode –  0: I2S mode, usedfor I2S, PCMand TDMprotocols
                   1: DIT mode, usedfor S/PDIF protocol

You might explore McASP driver (davinci-mcasp.c) how op-mode is handled.

simple-audio-card, format - CPU/CODEC common audio format. "i2s", "right_j", "left_j" , "dsp_a" "dsp_b", "ac97", "pdm", "msb", "lsb"

This format is handled in below 3 files:

linux-kernel/sound/soc/soc-core.c

linux-kernel/sound/soc/ti/davinci-mcasp.c

linux-kernel/sound/soc/codecs/tlv320aic3x.c

Check also below user guides which provides more info:

http://www.ti.com/lit/an/sprac09a/sprac09a.pdf

http://www.ti.com/lit/an/sprac10/sprac10.pdf

Regards,
Pavel

Regarding  DTS, I can see you are not fully aligned with AM572x TI EVM DTS file, where we have:

&mcasp3 {
    #sound-dai-cells = <0>;
    assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
    assigned-clock-parents = <&sys_clkin2>;
    status = "okay";

Can you make this update and then check again?

Regards,
Pavel

Hi Pavel

Thanks for your support

We will follow the way it is in AM5728-Gp-EVM.I have configured the MCLK through register write in last.c file.

after running the command

aplay -D hw:1,0 -f S16_LE -r48000 -c2 piano2.wav

following message is comming at console
Playing WAVE 'piano2.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Stereo
root@am57xx-evm:~# aplay -D hw:1,0 -f S16_LE -r48000 -c2 piano2.wav
Playing WAVE 'piano2.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Stereo

no audio at audio out

Then i ran a command

aplay -D hw:1,0 -f S16_LE -r48000 -c2 /dev/urandom &omapconf show

Playing raw data '/dev/urandom' : Signed 16 bit Little Endian, Rate 48000 Hz, So
OMAPCONF (rev v1.73 built Sat Apr 6 04:26:28 UTC 2019)

HW Platform:
Generic DRA72X (Flattened Device Tree)
DRA72X ES2.0 GP Device (STANDARD performance (1.0GHz))
Error: I2C Read failed
Error: I2C Read failed
Error: I2C Read failed
TPS65917 ES2.2

SW Build Details:
Build:
Version: _____ _____ _ _
Kernel:
Version: 4.14.79-ge669d52447
Author: bcg@BCGI142
Toolchain: gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11
Type: #1 SMP PREEMPT
Date: Thu Oct 24 17:31:29 IST 2019


NAME
omapconf - TI OMAP Configuration Diagnostic Tool

SYNOPSIS
omapconf [--version] [--help] [--cpuinfo] [--buildinfo] [--import <file]

See 'omapconf --help' for more information.

omapconf: powerdm_deinit(): cpu not supported!!!
omapconf: clockdm_deinit(): cpu not supported!!!

Some random noise are coming.

I have verified the frame clock and bit clock and working correctly

Regards

Satheesh Kumar S

satheesh kumar32 said:

Satheesh Kumar

satheesh kumar32 said:

after running the command

aplay -D hw:1,0 -f S16_LE -r48000 -c2 piano2.wav

following message is comming at console
Playing WAVE 'piano2.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Stereo
root@am57xx-evm:~# aplay -D hw:1,0 -f S16_LE -r48000 -c2 piano2.wav
Playing WAVE 'piano2.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Stereo

no audio at audio out

Please probe AM571x McASP pins (aclkx, fsx, axr0, clkout2) during aplay command and verify you have the correct signals there. You can compare with AM572x TI EVM McASP signals during aplay command execution.

If these signals are correct, then you nee to focus on tlv320aic3106 codec settings.

Regards,
Pavel

Hi pavel

Thanks for your quick reply

When I update the McASP node with above modification following error is occurred

 &mcasp3 {

#sound-dai-cells = <0>;
assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&sys_clkin2>;
status = "okay";

op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializers */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};

Error: arch/arm/boot/dts/am571x-idk.dts:105.36-37 syntax error
FATAL ERROR: Unable to parse input tree
scripts/Makefile.lib:317: recipe for target 'arch/arm/boot/dts/am571x-idk.dtb' failed
make[1]: *** [arch/arm/boot/dts/am571x-idk.dtb] Error 1
arch/arm/Makefile:353: recipe for target 'dtbs' failed
make: *** [dtbs] Error 2

Regards

Satheesh Kumar S

Satheesh Kumar S,

satheesh kumar32 said:

When I update the McASP node with above modification following error is occurred

 &mcasp3 {

#sound-dai-cells = <0>;
assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&sys_clkin2>;
status = "okay";

op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializers */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};

Error: arch/arm/boot/dts/am571x-idk.dts:105.36-37 syntax error

Do you use AM57x PSDK Linux? If yes, which version?

Latest version is 6.01, available at below link:

http://software-dl.ti.com/processor-sdk-linux/esd/AM57X/latest/index_FDS.html

Regards,
Pavel

Hi Pavel

Thanks lot

I have verified the aclkx, fsx, axr0, clkout2 and it works as expected.

yesterdy, i was mistaken.No volume is due to less PGA gain at output

Now aplay -D hw:1,0 -f S16_LE -r48000 -c2 piano2.wav working correctly.

But recording have some problem

when I playback after recording no sound is coming.Now I am looking in to that.

please comment about these issue

Regards

Satheesh Kumar S

Hi Pavel

I have one more doubt

If I divide the system clock from 24.576MHz to 12.288MHz,bit clock  and frame clock are also divided by 2.Why  this happened ?

Plz help

Regrads

Satheesh Kumar S

Satheesh Kumar S,

satheesh kumar32 said:

I have verified the aclkx, fsx, axr0, clkout2 and it works as expected.

satheesh kumar32 said:

Now aplay -D hw:1,0 -f S16_LE -r48000 -c2 piano2.wav working correctly.

But recording have some problem

On AM572x TI EVM, audio is received from AIC3x codec MIC2L/MIC2R pins. How about your custom board?

During arecord execution, you need to probe with scope AM571x McASP pins aclkx, fsx, axr1, clkout2 and verify these have correct signals. You can compare with AM572x EVM.

Regards,
Pavel

satheesh kumar32 said:

I have one more doubt

If I divide the system clock from 24.576MHz to 12.288MHz,bit clock  and frame clock are also divided by 2.Why  this happened ?

Plz help

Seems that McASP3 bit clock (aclkx) and FS (afsx) are based on sys_clk2 (OSC1 24.576MHz), not on sys_clk1 (OSC0 20MHz). You can check and confirm this through dump and explore below registers values (during aplay/arecord):

CM_L4PER_MCASP3_CLKCTRL

CM_CLKSEL_PER_ABE_X1_GFCLK_AUX
CM_CLKSEL_ABE_PLL_REF
CM_CLKSEL_ABE_PLL_SYS

MCASP3.MCASP_AHCLKXCTL
MCASP3.MCASP_ACLKXCTL

Regards,
Pavel

Hi Pavel

Thanks lot

We need master clcok 12.288MHz which is derived from 24.576MHz(external oscillator)

CM_L4PER2_MCASP3_CLKCTRL
root@am57xx-evm:~# devmem2 0x4A009868
/dev/mem opened.
Memory mapped at address 0xb6f35000.
Read at address 0x4A009868 (0xb6f35868): 0x07030000
CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX
root@am57xx-evm:~# devmem2 0x4AE06138
/dev/mem opened.
Memory mapped at address 0xb6f77000.
Read at address 0x4AE06138 (0xb6f77138): 0x00000000
CM_CLKSEL_ABE_PLL_REF
root@am57xx-evm:~# devmem2 0x4AE0610C
/dev/mem opened.
Memory mapped at address 0xb6f25000.
Read at address 0x4AE0610C (0xb6f2510c): 0x00000000
CM_CLKSEL_ABE_PLL_SYS
root@am57xx-evm:~# devmem2 0x4AE06118
/dev/mem opened.
Memory mapped at address 0xb6f1a000.
Read at address 0x4AE06118 (0xb6f1a118): 0x00000000

while reading MCASP_AHCLKXCTL following error are comming

root@am57xx-evm:~# devmem2 0x484680B0
/dev/mem opened.[ 3901.328709] ------------[ cut here ]------------
[ 3901.334684] WARNING: CPU: 0 PID: 1111 at drivers/bus/omap_l3_noc.c:147 l3_in0
[ 3901.344119] 44000000.ocp:L3 Custom Error: MASTER MPU TARGET L4_PER2_P3 (Reads
[ 3901.355731] Modules linked in: sha512_generic sha512_arm sha256_generic sha1)
[ 3901.427995] cryptodev(O) cmemk(O)
[ 3901.431423] CPU: 0 PID: 1111 Comm: devmem2 Tainted: G W O 4.14.791
[ 3901.439809] Hardware name: Generic DRA72X (Flattened Device Tree)
[ 3901.445926] Backtrace:
[ 3901.448392] [<c020b4dc>] (dump_backtrace) from [<c020b7c0>] (show_stack+0x18)
[ 3901.455996] r7:00000009 r6:600b0193 r5:00000000 r4:c1054750
[ 3901.461688] [<c020b7a8>] (show_stack) from [<c0933ae8>] (dump_stack+0x90/0xa)
[ 3901.468945] [<c0933a58>] (dump_stack) from [<c022b9cc>] (__warn+0xec/0x104)
[ 3901.475937] r7:00000009 r6:c0bd78ac r5:00000000 r4:ee449dd0
[ 3901.481621] [<c022b8e0>] (__warn) from [<c022ba24>] (warn_slowpath_fmt+0x40/)
[ 3901.489138] r9:0000001a r8:ef1ba790 r7:c0bd7718 r6:00000002 r5:c0bd77d8 r4:c
[ 3901.496916] [<c022b9e8>] (warn_slowpath_fmt) from [<c051bd20>] (l3_interrupt)
[ 3901.505825] r3:ef1ba600 r2:c0bd787c
[ 3901.509414] r4:80080003
[ 3901.511961] [<c051bacc>] (l3_interrupt_handler) from [<c027f5a4>] (__handle_)
[ 3901.521483] r10:c105614d r9:ef1b8200 r8:00000017 r7:ee449ef4 r6:00000000 r50
[ 3901.529345] r4:ef1bab00
[ 3901.531892] [<c027f538>] (__handle_irq_event_percpu) from [<c027f690>] (hand)
[ 3901.541588] r10:00000002 r9:00000001 r8:ef008000 r7:00000000 r6:c10093ac r50
[ 3901.549448] r4:ef1b8200
[ 3901.551994] [<c027f66c>] (handle_irq_event_percpu) from [<c027f70c>] (handle)
[ 3901.560904] r5:ef1b8264 r4:ef1b8200
[ 3901.564500] [<c027f6cc>] (handle_irq_event) from [<c0283020>] (handle_fasteo)
[ 3901.573062] r7:00000000 r6:c10093ac r5:ef1b8264 r4:ef1b8200
[ 3901.578748] [<c0282f74>] (handle_fasteoi_irq) from [<c027e7f4>] (generic_han)
[ 3901.587397] r7:00000000 r6:00000000 r5:00000017 r4:c0e64b3c
[ 3901.593083] [<c027e7c8>] (generic_handle_irq) from [<c027ed7c>] (__handle_do)
[ 3901.601820] [<c027ed18>] (__handle_domain_irq) from [<c0201474>] (gic_handle)
[ 3901.610209] r9:00000001 r8:fa213000 r7:fa212000 r6:ee449fb0 r5:fa21200c r4:0
[ 3901.617988] [<c0201430>] (gic_handle_irq) from [<c020c6e8>] (__irq_usr+0x48/)
[ 3901.625501] Exception stack(0xee449fb0 to 0xee449ff8)
[ 3901.630574] 9fa0: 000103e3 b6fd1960 be988
[ 3901.638788] 9fc0: 00000000 00021048 b6fced40 be9859a8 000103e3 00000001 00000
[ 3901.647000] 9fe0: 000103cc be985988 b6fb3efb b6fb0286 200b0030 ffffffff
[ 3901.653643] r9:00000001 r8:30c5387d r7:30c5387d r6:ffffffff r5:200b0030 r4:6
[ 3901.661418] ---[ end trace 90e4b9b301709313 ]---

Memory mapped at address 0xb6fcd000.
[ 3901.666231] Unhandled fault: asynchronous external abort (0x1211) at 0x000000
[ 3901.676944] pgd = ee661fc0
[ 3901.679661] [00000000] *pgd=ad3cc003, *pmd=00000000
Read at address 0x484680B0 (0xb6fcd0b0): 0x00000000
root@am57xx-evm:~# [ 3901.721961] systemd[1]: systemd-journald.service: Failed .
[ 3901.750405] systemd[1]: systemd-journald.service: Service has no hold-off ti.
[ 3901.762771] systemd[1]: Stopped Flush Journal to Persistent Storage.
[ 3901.769793] systemd[1]: Stopping Flush Journal to Persistent Storage...
[ 3901.777676] systemd[1]: Stopped Journal Service.
[ 3901.791240] systemd[1]: Starting Journal Service...
[ 3901.874226] systemd-journald[1113]: File /run/log/journal/071078bfe21349d888.
[ 3901.937842] systemd[1]: Started Journal Service.
[ 3902.380897] systemd-coredump[1112]: MESSAGE=Process 1108 (systemd-journal) o.
[ 3902.389820] systemd-coredump[1112]: Coredump diverted to /var/lib/systemd/coz

Regards

Satheesh Kumar S

Satheesh Kumar S,

satheesh kumar32 said:

We need master clcok 12.288MHz which is derived from 24.576MHz(external oscillator)

You need to provide 12.288Mhz master clock (derive from 24.576MHz ext osc) to AM571x McASP3 module or external audio codec AIC3x?

satheesh kumar32 said:

CM_L4PER2_MCASP3_CLKCTRL
root@am57xx-evm:~# devmem2 0x4A009868
/dev/mem opened.
Memory mapped at address 0xb6f35000.
Read at address 0x4A009868 (0xb6f35868): 0x07030000
CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX
root@am57xx-evm:~# devmem2 0x4AE06138
/dev/mem opened.
Memory mapped at address 0xb6f77000.
Read at address 0x4AE06138 (0xb6f77138): 0x00000000
CM_CLKSEL_ABE_PLL_REF
root@am57xx-evm:~# devmem2 0x4AE0610C
/dev/mem opened.
Memory mapped at address 0xb6f25000.
Read at address 0x4AE0610C (0xb6f2510c): 0x00000000
CM_CLKSEL_ABE_PLL_SYS
root@am57xx-evm:~# devmem2 0x4AE06118
/dev/mem opened.
Memory mapped at address 0xb6f1a000.
Read at address 0x4AE06118 (0xb6f1a118): 0x00000000

while reading MCASP_AHCLKXCTL following error are comming

You need to make that register dump during arecord command execution, or recording userspace application execution.

Regards,
Pavel

Hi Pavel

Thanks for your reply

I our custom design,system clock 1 is 20MHz and system clock 2 is 24.576MHz(exclusively for audio).

I have a plan to operate audio codec at rate of 12.288(MCLK).That is why I am asking this question.

How to make register dump during recording(terminal is busy during arecord)

or did you mean

root@am57xx-evm:~# arecord test.wav & omapconf dump mcasp3
[1] 1090
Recording WAVE 'test.wav' : Unsigned 8 bit, Rate 8000 Hz, Mono
OMAPCONF (rev v1.73 built Sat Apr 6 04:26:28 UTC 2019)

Regards

Satheesh Kumar S

HW Platform:
Generic DRA72X (Flattened Device Tree)
DRA72X ES2.0 GP Device (STANDARD performance (1.0GHz))
Error: I2C Read failed
Error: I2C Read failed
Error: I2C Read failed
TPS65917 ES2.2

SW Build Details:
Build:
Version: _____ _____ _ _
Kernel:
Version: 4.14.79-ge669d52447
Author: bcg@BCGI142
Toolchain: gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11
Type: #1 SMP PREEMPT
Date: Wed Nov 13 15:35:00 IST 2019

|--------------------------------------------|
| Reg. Name | Reg. Addr | Reg. Val. |
|--------------------------------------------|
| MCASP_PID | 0x48468000 | 0x44307B03 |
| PWRIDLESYSCONFIG | 0x48468004 | 0x00000002 |
| MCASP_PFUNC | 0x48468010 | 0x00000000 |
| MCASP_PDIR | 0x48468014 | 0x00000001 |
| MCASP_PDOUT | 0x48468018 | 0x00000000 |
| MCASP_PDIN | 0x4846801C | 0x00000002 |
| MCASP_PDCLR | 0x48468020 | 0x00000000 |
| MCASP_GBLCTL | 0x48468044 | 0x0000001E |
| MCASP_AMUTE | 0x48468048 | 0x00000000 |
| MCASP_LBCTL | 0x4846804C | 0x00000000 |
| MCASP_TXDITCTL | 0x48468050 | 0x00000000 |
| MCASP_GBLCTLR | 0x48468060 | 0x0000001F |
| MCASP_RXMASK | 0x48468064 | 0x0000FFFF |
| MCASP_RXFMT | 0x48468068 | 0x00008070 |
| MCASP_RXFMCTL | 0x4846806C | 0x00000100 |
| MCASP_ACLKRCTL | 0x48468070 | 0x00180000 |
| MCASP_AHCLKRCTL | 0x48468074 | 0x00000000 |
| MCASP_RXTDM | 0x48468078 | 0x00000003 |
| MCASP_EVTCTLR | 0x4846807C | 0x00000001 |
| MCASP_RXSTAT | 0x48468080 | 0x0000015C |
| MCASP_RXTDMSLOT | 0x48468084 | 0x00000001 |
| MCASP_RXCLKCHK | 0x48468088 | 0x00000000 |
| MCASP_REVTCTL | 0x4846808C | 0x00000000 |
| MCASP_GBLCTLX | 0x484680A0 | 0x0000001F |
| MCASP_TXMASK | 0x484680A4 | 0x0000FFFF |
| MCASP_TXFMT | 0x484680A8 | 0x00000074 |
| MCASP_TXFMCTL | 0x484680AC | 0x00000000 |
| MCASP_ACLKXCTL | 0x484680B0 | 0x00180000 |
| MCASP_AHCLKXCTL | 0x484680B4 | 0x00180000 |
| MCASP_TXTDM | 0x484680B8 | 0x00000000 |
| MCASP_EVTCTLX | 0x484680BC | 0x00000000 |
| MCASP_TXSTAT | 0x484680C0 | 0x0000010C |
| MCASP_TXTDMSLOT | 0x484680C4 | 0x0000017F |
| MCASP_TXCLKCHK | 0x484680C8 | 0x00000000 |
| MCASP_XEVTCTL | 0x484680CC | 0x00000000 |
| MCASP_CLKADJEN | 0x484680D0 | 0x00000000 |
| MCASP_XRSRCTL0 | 0x48468180 | 0x00000019 |
| MCASP_XRSRCTL1 | 0x48468184 | 0x00000002 |
| MCASP_XRSRCTL2 | 0x48468188 | 0x00000000 |
| MCASP_XRSRCTL3 | 0x4846818C | 0x00000000 |
| MCASP_WFIFOCTL | 0x48469000 | 0x00001004 |
| MCASP_WFIFOSTS | 0x48469004 | 0x00000000 |
| MCASP_RFIFOCTL | 0x48469008 | 0x00011901 |
| MCASP_RFIFOSTS | 0x4846900C | 0x00000007 |
|--------------------------------------------|

Regards

Satheesh Kumar S

HI Pavel

Thanks lot

First experiment

In our design sys_clk2 (OSC1 24.576MHz) -->clkout2 pin (24.576MHz) -> AIC3x MCLK

When I start doing aplay/arecord biclock =1.536MHz and frame clock = 48KHz

It is expected one and we get proper recording and playback.No kernel source modification only device tree modification.If codec is master, bitclock and frame clock are generated by audio codec not McASP. So why this clock division in McASP register(I am sorry if am wrong)

second experiment

sys_clk2 (OSC1 24.576MHz) -->clkout2 pin (24.576MHz/2---->12.288MHz) -> AIC3x MCLK(verified the clockout2 12.288MHz)

When I start doing aplay/arecord biclock =768KHz and frame clock = 24KHz.

This is for my exact issue 

Regards

Satheesh KUmar S

satheesh kumar32 said:

First experiment

In our design sys_clk2 (OSC1 24.576MHz) -->clkout2 pin (24.576MHz) -> AIC3x MCLK

When I start doing aplay/arecord biclock =1.536MHz and frame clock = 48KHz

It is expected one and we get proper recording and playback.No kernel source modification only device tree modification.If codec is master, bitclock and frame clock are generated by audio codec not McASP. So why this clock division in McASP register(I am sorry if am wrong)

Regarding this first experiment.

From what I understand (correct me if I am wrong), AM571x McASP3 is slave, AIC3x codec is master. AIC3x codec receive 24.567MHz clock source from MCLK input and produce bit clock and frame clock based on this MCLK, through AIC3x internal dividers and/or multipliers. For more info, check AIC3x documents. When AIC3x is master, it produce the bit clock and frame sync, the division is made in AIC3x registers, not in McASP3 registers.

You can only divide sys_clk2 before it reaches the clkout2 pin. This division is made in AM571x PRCM register, not in McASP3 module register.

CM_CLKSEL_SYS_CLK2_CLKOUTMUX[2:0] CLKSEL = 0x0 (Select CLK divided by 1)

                                                                  [2:0] CLKSEL = 0x1 (Select CLK divided by 2)

satheesh kumar32 said:

second experiment

sys_clk2 (OSC1 24.576MHz) -->clkout2 pin (24.576MHz/2---->12.288MHz) -> AIC3x MCLK(verified the clockout2 12.288MHz)

When I start doing aplay/arecord biclock =768KHz and frame clock = 24KHz.

This is for my exact issue 

In this second experiment, do you still have AM571x McASP3 slave, AIC3x codec master? If yes, then the problem is in AIC3x codec settings (registers, dividers, multipliers). Seems that AIC3x codec can produce correct bit clock and frame sync from 24.576MHz clock input, but not from 12.288MHz clock input. You will need to check AIC3x documentation and source code regarding what values of MCLK are supported for its linux driver.

Regards,
Pavel

Hi Pavel

Thanks lot

You are correct.

In second experiment clockout2(12.288MHz) is generated by register writing in kernel source directly

CM_CLKSEL_SYS_CLK2_CLKOUTMUX[2:0] CLKSEL =  [2:0] CLKSEL = 0x1 (Select CLK divided by 2)

Regards

Satheesh Kumar S

Satheesh Kumar S,

Do you have more questions related to subject of this e2e thread?

Regards,
Pavel