AM5718: CLKOUT2 issue

satheesh kumar32

Expert 1045 points

Part Number: AM5718
Other Parts Discussed in Thread: TLV320AIC3104, , TLV320AIC3106, BEAGLEBOARD-X15

Hello

I am working in AM5718-idk.

I have a requirement to route system clock(20MHz) to clkout2 pin.

I have modified the mux_data.h file in u-boot for clkout2.

In device tree (dra7xx-clocks.dtsi),I have modified the clock divider node to

sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&sys_clkin1>;
  ti,max-div = <1>;
  reg = <0x01c8>;
  ti,index-power-of-two;
};

After booting, when I probe the pin(R893 or R220),nothing is coming.

is anything more to be done for routing system clock to clock pin?

In above clock division node (sys_clk1_dclk_div), clock input is clocks = <&sys_clkin1>; and is defined in prm_clocks node

&prm_clocks {
sys_clkin1: sys_clkin1@110 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
  reg = <0x0110>;
  ti,index-starts-at-one;
};

which clock is routed to clock divider node? can you explain it

Regards

Satheesh Kumar S

over 6 years ago

0 Pavel Botev over 6 years ago

TI__Guru**** 170625 points

Hi Satheesh,

I would suggest you to dump the clkout2 related register and check their values.

CTRL_CORE_PAD_GPMC_ADVN_ALE/0x4A0034C4

CTRL_CORE_PAD_XREF_CLK0/0x4A003694

CM_COREAON_CLKOUTMUX2_CLKCTRL/0x4A0086B0

CM_CLKSEL_CLKOUTMUX2/0x4AE06160

CM_CLKSEL_SYS_CLK1_CLKOUTMUX/0x4AE061C8

If some value is not correct, you need to update u-boot/kernel code base to get the correct values in these registers.

Regards,
Pavel

0 satheesh kumar32 over 6 years ago in reply to Pavel Botev

Expert 1045 points

Hi Pavel

Thanks for your support.

I have checked the all the register values .Only below mentioned register showing unexpected value.

CM_COREAON_CLKOUTMUX2_CLKCTRL/0x4A0086B0 : 0x00000000

The expected value is 0x00000100.Then I update the register with value 00000100,we got clock(20MHz) at clockout2.

I think the statement ti,bit-shift = <8>; in device tree have no effect.

clkout2_clk: clkout2_clk@6b0 {
  #clock-cells = <0>;
  compatible = "ti,gate-clock";
  clocks = <&clkoutmux2_clk_mux>;
  ti,bit-shift = <8>;
  reg = <0x06b0>;
};

Please suggest how to solve this issue.

Regards

Satheesh Kumar S

0 Pavel Botev over 6 years ago in reply to satheesh kumar32

TI__Guru**** 170625 points

Satheesh,

In your DTS file, you need to use "assigned-clocks" and "clocks" entries. For example, you can refer to AM572x TI EVM, where pin D18 clkout2 is used to provide sys_clk2 clock to external AIC3x audio codec.

am57xx-beagle-x15-common.dtsi

tlv320aic3104: tlv320aic3104@18 {

assigned-clocks = <&clkoutmux2_clk_mux>;
assigned-clock-parents = <&sys_clk2_dclk_div>;

}

sound0_master: simple-audio-card,codec {
           sound-dai = <&tlv320aic3104>;
           clocks = <&clkout2_clk>;
       };

Regards,
Pavel

0 satheesh kumar32 over 6 years ago in reply to Pavel Botev

Expert 1045 points

Hi Pavel

Thanks for your instant support.

I have modified the dtsi file(dra7xx-clocks.dtsi)

clkout2_clk: clkout2_clk@6b0 {
  #clock-cells = <0>;
  compatible = "ti,gate-clock";
  assigned-clocks = <&clkoutmux2_clk_mux>;
  assigned-clock-parents=<&sys_clk1_dclk_div>;
  reg = <0x06b0>;
};

But still it is not working. I am only beginner in this area.

Regards

Satheesh Kumar

0 Pavel Botev over 6 years ago in reply to satheesh kumar32

TI__Guru**** 170625 points

Satheesh,

Not this (dra7xx-clocks.dtsi) file. You need to modify your main DTS file. For example, AM571x IDK main DTS file is am571x-idk.dts. And you need to add:

assigned-clocks = <&clkoutmux2_clk_mux>;

assigned-clock-parents=<&sys_clk1_dclk_div>;

clocks = <&clkout2_clk>

Regards,
Pavel

0 satheesh kumar32 over 6 years ago in reply to Pavel Botev

Expert 1045 points

Hi Pavel

Thanks for your instant support.

But that file contain only some limited nodes

/dts-v1/;

#include "am571x-idk-common.dtsi"

/ {
model = "TI AM5718 IDK";

aliases {
ethernet4 = &pruss1_emac0;
ethernet5 = &pruss1_emac1;
};

/* Dual mac ethernet application node on icss2 */
pruss1_eth: pruss1_eth {
  status = "disabled";
  compatible = "ti,am57-prueth";
  prus = <&pru1_0>, <&pru1_1>;
  firmware-name = "ti-pruss/am57xx-pru0-prueth-fw.elf",
    "ti-pruss/am57xx-pru1-prueth-fw.elf";
  ti,pruss-gp-mux-sel = <0>, /* GP, default */
          <4>; /* MII2, needed for PRUSS1_MII1 */
  sram = <&ocmcram1>;
  interrupt-parent = <&pruss1_intc>;
  interrupts = <20>, <21>;
  interrupt-names = "rx_red_hp", "rx_red_lp";

  pruss1_emac0: ethernet-mii0 {
   phy-handle = <&pruss1_eth0_phy>;
   phy-mode = "mii";
   interrupts = <20>, <22>, <23>, <26>;
   interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
       "emac_ptp_tx";
   /* Filled in by bootloader */
   local-mac-address = [00 00 00 00 00 00];
  };

  pruss1_emac1: ethernet-mii1 {
   phy-handle = <&pruss1_eth1_phy>;
   phy-mode = "mii";
   interrupts = <21>, <23>, <24>, <27>;
   interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
       "emac_ptp_tx";
   /* Filled in by bootloader */
   local-mac-address = [00 00 00 00 00 00];
  };
};
};

&pruss1_mdio {
status = "disabled";
reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
pruss1_eth0_phy: ethernet-phy@0 {
  reg = <0>;
  interrupt-parent = <&gpio3>;
  interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
};

pruss1_eth1_phy: ethernet-phy@1 {
  reg = <1>;
  interrupt-parent = <&gpio3>;
  interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
};
};

&pruss2_eth {
ti,pruss-gp-mux-sel = <4>, /* MII2, needed for PRUSS1_MII0 */
<4>; /* MII2, needed for PRUSS1_MII1 */
};

#include "am57xx-evm-cmem-am571x.dtsi"

Regards

Satheesh Kumar S

0 Pavel Botev over 6 years ago in reply to satheesh kumar32

TI__Guru**** 170625 points

Satheesh,

To what king of external device you are attaching clkout2 pin? Do you describe this external device in your DTS file?

In AM572x TI EVM, this pin is used for audio purpose, and goes into AIC3x codec. Thus McASP and AIC3x nods are used with these clkout2 entries. You need to update the node that is using clkout2 pin.

If you do not attach clkout2 pin to anything, you might create a dummy node or modify some already existing node like pruss1_eth

Regards,
Pavel

0 satheesh kumar32 over 6 years ago in reply to Pavel Botev

Expert 1045 points

Hi Pavel

Thanks for your instant support.

Ok understood

Actually we have plan to interface audio codec(tlv320AIC) with AM571xbased custom board .But it is still development phase. We have a plan to interface AM571xidk with TLV320 AIC evm for initial validation.

One more question

Suppose I need a system clock divided by 2.What are the modification that I need to do in device tree.?

Once again thanks for your help.

Regards

Satheesh Kumar S

0 satheesh kumar32 over 6 years ago in reply to satheesh kumar32

Expert 1045 points

Hi Pavel

I have added following snippet to am571x-idk.dts file

test {

assigned-clocks = <&clkoutmux2_clk_mux>;

assigned-clock-parents=<&sys_clk1_dclk_div>;

clocks = <&clkout2_clk>

};

but I cant compile this.

I want to update the register

CM_COREAON_CLKOUTMUX2_CLKCTRL/0x4A0086B0 : 0x00000100

CM_CLKSEL_SYS_CLK1_CLKOUTMUX/0x4AE0 61C8:0x0000001 for Select CLK divided by 2

finally i need 10MHz clock at clockout2 pin

please suggest the device tree modification

I have tested this with manually wrote these register and verified the clock.

Regards

Satheesh Kumar S

0 Pavel Botev over 6 years ago in reply to satheesh kumar32

TI__Guru**** 170625 points

Satheesh,

satheesh kumar32 said:

One more question

Suppose I need a system clock divided by 2.What are the modification that I need to do in device tree.?

You can try with "assigned-clock-rates" entry. You can assign 10MHz to that entry, and the divider value should be set automatically based on the rate value. You can use "assigned-clock-rates" entry in the same node as "assigned-clock-parents" and "assigned-clocks"

For example of that entry usage, you can refer to below files:

linux-4.19.38Documentation/devicetree/bindings/clock/clock-bindings.txt

linux-4.19.38/arch/arm/boot/dts/dra76x.dtsi

Regards,
Pavel

0 satheesh kumar32 over 6 years ago in reply to Pavel Botev

Expert 1045 points

Hi Pavel

Thanks for your reply

test {
   assigned-clocks = <&clkoutmux2_clk_mux>;
   assigned-clock-parents = <&sys_clk1_dclk_div>;
   assigned-clock-rates = <10000000>;
   clocks = <&clkout2_clk>;
   };

when i compiled,following error is comming

Error: arch/arm/boot/dts/am571x-idk.dts:77.1-5 syntax error
FATAL ERROR: Unable to parse input tree
scripts/Makefile.lib:317: recipe for target 'arch/arm/boot/dts/am571x-idk.dtb' failed
make[1]: *** [arch/arm/boot/dts/am571x-idk.dtb] Error 1
arch/arm/Makefile:353: recipe for target 'dtbs' failed
make: *** [dtbs] Error 2
Regards

Satheesh Kumar S

0 satheesh kumar32 over 6 years ago in reply to satheesh kumar32

Expert 1045 points

hello pavel

A gentle reminder

Regards

Satheesh Kumar S

0 satheesh kumar32 over 6 years ago in reply to satheesh kumar32

Expert 1045 points

Hi Pavel

Is this is the format to write dummy device node?

test {
   assigned-clocks = <&clkoutmux2_clk_mux>;
   assigned-clock-parents = <&sys_clk1_dclk_div>;
   assigned-clock-rates = <10000000>;
   clocks = <&clkout2_clk>;
   };

Regards

Satheesh Kumar S

0 Pavel Botev over 6 years ago in reply to satheesh kumar32

TI__Guru**** 170625 points

Satheesh,

satheesh kumar32 said:
test {
   assigned-clocks = <&clkoutmux2_clk_mux>;
   assigned-clock-parents = <&sys_clk1_dclk_div>;
   assigned-clock-rates = <10000000>;
   clocks = <&clkout2_clk>;
   };

This does not look correct.

satheesh kumar32 said:
Error: arch/arm/boot/dts/am571x-idk.dts:77.1-5 syntax error

Can you attach your full am571x-idk.dts file for review?

Regards,
Pavel

0 satheesh kumar32 over 6 years ago in reply to Pavel Botev

Expert 1045 points

Hi Pavel

I am attaching full am571x-idk.dts

Fullscreen 6558.am571x-idk.txt Download

/*
 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "am571x-idk-common.dtsi"

/ {
	model = "TI AM5718 IDK";

	aliases {
		ethernet4 = &pruss1_emac0;
		ethernet5 = &pruss1_emac1;
	};

	/* Dual mac ethernet application node on icss2 */
	pruss1_eth: pruss1_eth {
		status = "okay";
		compatible = "ti,am57-prueth";
		prus = <&pru1_0>, <&pru1_1>;
		firmware-name = "ti-pruss/am57xx-pru0-prueth-fw.elf",
				"ti-pruss/am57xx-pru1-prueth-fw.elf";
		ti,pruss-gp-mux-sel = <0>,	/* GP, default */
				      <4>;	/* MII2, needed for PRUSS1_MII1 */
		sram = <&ocmcram1>;
		interrupt-parent = <&pruss1_intc>;
		interrupts = <20>, <21>;
		interrupt-names = "rx_red_hp", "rx_red_lp";

		pruss1_emac0: ethernet-mii0 {
			phy-handle = <&pruss1_eth0_phy>;
			phy-mode = "mii";
			interrupts = <20>, <22>, <23>, <26>;
			interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
					  "emac_ptp_tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};

		pruss1_emac1: ethernet-mii1 {
			phy-handle = <&pruss1_eth1_phy>;
			phy-mode = "mii";
			interrupts = <21>, <23>, <24>, <27>;
			interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
					  "emac_ptp_tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};
	};
};

&pruss1_mdio {
	status = "okay";
	reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
	pruss1_eth0_phy: ethernet-phy@0 {
		reg = <0>;
		interrupt-parent = <&gpio3>;
		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
	};

	pruss1_eth1_phy: ethernet-phy@1 {
		reg = <1>;
		interrupt-parent = <&gpio3>;
		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
	};
};

&pruss2_eth {
	ti,pruss-gp-mux-sel = <4>,	/* MII2, needed for PRUSS1_MII0 */
			      <4>;	/* MII2, needed for PRUSS1_MII1 */
};

test {
	assigned-clocks = <&clkoutmux2_clk_mux>;
	assigned-clock-parents = <&sys_clk1_dclk_div>;
	assigned-clock-rates = <10000000>;
	clocks = <&clkout2_clk>;
	};
#include "am57xx-evm-cmem-am571x.dtsi"

0 Pavel Botev over 6 years ago in reply to satheesh kumar32

TI__Guru**** 170625 points

Satheesh,

I would suggest you to try something like below:

#include "am571x-idk-common.dtsi"

/ {
   model = "TI AM5718 IDK";

   aliases {
       ethernet4 = &pruss1_emac0;
       ethernet5 = &pruss1_emac1;
        + sound0 = &sound0;
   };

+ sound0: sound0 {

+ assigned-clocks = <&clkoutmux2_clk_mux>;
+ assigned-clock-parents = <&sys_clk1_dclk_div>;
+ assigned-clock-rates = <10000000>;
+ clocks = <&clkout2_clk>;

+ };

/* Dual mac ethernet application node on icss2 */
pruss1_eth: pruss1_eth {

Regards,
Pavel

0 satheesh kumar32 over 6 years ago in reply to Pavel Botev

Expert 1045 points

Hi Pavel

Thanks for your reply

I have modified the AM571x-idk.dts file based on your suggestion.

But still it is not working.

I have read the register (4a0086b0),still it is showing 0 value .

I am attaching the modified dts file.

Regards

Satheesh Kumar S

Fullscreen 8156.am571x-idk.txt Download

/*
 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "am571x-idk-common.dtsi"

/ {
	model = "TI AM5718 IDK";

	aliases {
		ethernet4 = &pruss1_emac0;
		ethernet5 = &pruss1_emac1;
		 sound0 = &sound0;
	};
	sound0: sound0 {
	assigned-clocks = <&clkoutmux2_clk_mux>;
	assigned-clock-parents = <&sys_clk1_dclk_div>;
	assigned-clock-rates = <10000000>;
	clocks = <&clkout2_clk>;
	 };




	/* Dual mac ethernet application node on icss2 */
	pruss1_eth: pruss1_eth {
		status = "disabled";
		compatible = "ti,am57-prueth";
		prus = <&pru1_0>, <&pru1_1>;
		firmware-name = "ti-pruss/am57xx-pru0-prueth-fw.elf",
				"ti-pruss/am57xx-pru1-prueth-fw.elf";
		ti,pruss-gp-mux-sel = <0>,	/* GP, default */
				      <4>;	/* MII2, needed for PRUSS1_MII1 */
		sram = <&ocmcram1>;
		interrupt-parent = <&pruss1_intc>;
		interrupts = <20>, <21>;
		interrupt-names = "rx_red_hp", "rx_red_lp";

		pruss1_emac0: ethernet-mii0 {
			phy-handle = <&pruss1_eth0_phy>;
			phy-mode = "mii";
			interrupts = <20>, <22>, <23>, <26>;
			interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
					  "emac_ptp_tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};

		pruss1_emac1: ethernet-mii1 {
			phy-handle = <&pruss1_eth1_phy>;
			phy-mode = "mii";
			interrupts = <21>, <23>, <24>, <27>;
			interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
					  "emac_ptp_tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};
	};
};

&pruss1_mdio {
	status = "disabled";
	reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
	pruss1_eth0_phy: ethernet-phy@0 {
		reg = <0>;
		interrupt-parent = <&gpio3>;
		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
	};

	pruss1_eth1_phy: ethernet-phy@1 {
		reg = <1>;
		interrupt-parent = <&gpio3>;
		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
	};
};

&pruss2_eth {
	ti,pruss-gp-mux-sel = <4>,	/* MII2, needed for PRUSS1_MII0 */
			      <4>;	/* MII2, needed for PRUSS1_MII1 */
};

#include "am57xx-evm-cmem-am571x.dtsi"

0 satheesh kumar32 over 6 years ago in reply to satheesh kumar32

Expert 1045 points

hello pavel

A gentle reminder

Regards

Satheesh Kumar S

0 Pavel Botev over 6 years ago in reply to satheesh kumar32

TI__Guru**** 170625 points

satheesh kumar32 said:

I have modified the AM571x-idk.dts file based on your suggestion.

But still it is not working.

Make sure you are creating new DTB file successful, and then loading this new DTB file that is based on your updated DTS file.

Are all other registers (0x4AE06160 and 0x4AE061C8) have the correct values?

Please try to modify your DTS file like below:

#include "am571x-idk-common.dtsi"

/ {
   model = "TI AM5718 IDK";

   aliases {
       ethernet4 = &pruss1_emac0;
       ethernet5 = &pruss1_emac1;
        + sound0 = &sound0;
   };

+ sound0: sound0 {

+ compatible = "simple-audio-card";

+ simple-audio-card,bitclock-master = <&sound0_master>;
+ simple-audio-card,frame-master = <&sound0_master>;

+ assigned-clocks = <&clkoutmux2_clk_mux>;
+ assigned-clock-parents = <&sys_clk1_dclk_div>;
+ assigned-clock-rates = <10000000>;

   + sound0_master: simple-audio-card,codec {
           + clocks = <&clkout2_clk>;
    +    };

+ };

/* Dual mac ethernet application node on icss2 */
pruss1_eth: pruss1_eth {

Regards,
Pavel

0 satheesh kumar32 over 6 years ago in reply to Pavel Botev

Expert 1045 points

Hi Pavel

Thanks for your continuous support.

I have modified the dts file based on your suggestion and no signal at CLOCKOUT2 pin.

I have read the register

0x4AE06160:0x00000000

0x4AE061C8:0x00000000

I am attaching modified original dts file

Fullscreen 1447.am571x-idk.txt Download

/*
 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "am571x-idk-common.dtsi"

/ {
	model = "TI AM5718 IDK";

	aliases {
		ethernet4 = &pruss1_emac0;
		ethernet5 = &pruss1_emac1;
  		sound0 = &sound0;
	};
	sound0: sound0 {
	compatible = "simple-audio-card";
 	simple-audio-card,bitclock-master = <&sound0_master>;
	simple-audio-card,frame-master = <&sound0_master>;
 	assigned-clocks = <&clkoutmux2_clk_mux>;
 	assigned-clock-parents = <&sys_clk1_dclk_div>;
  	assigned-clock-rates = <10000000>;
   	sound0_master: simple-audio-card,codec {
        clocks = <&clkout2_clk>;
    	};
 	};

	/* Dual mac ethernet application node on icss2 */
	pruss1_eth: pruss1_eth {
		status = "disabled";
		compatible = "ti,am57-prueth";
		prus = <&pru1_0>, <&pru1_1>;
		firmware-name = "ti-pruss/am57xx-pru0-prueth-fw.elf",
				"ti-pruss/am57xx-pru1-prueth-fw.elf";
		ti,pruss-gp-mux-sel = <0>,	/* GP, default */
				      <4>;	/* MII2, needed for PRUSS1_MII1 */
		sram = <&ocmcram1>;
		interrupt-parent = <&pruss1_intc>;
		interrupts = <20>, <21>;
		interrupt-names = "rx_red_hp", "rx_red_lp";

		pruss1_emac0: ethernet-mii0 {
			phy-handle = <&pruss1_eth0_phy>;
			phy-mode = "mii";
			interrupts = <20>, <22>, <23>, <26>;
			interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
					  "emac_ptp_tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};

		pruss1_emac1: ethernet-mii1 {
			phy-handle = <&pruss1_eth1_phy>;
			phy-mode = "mii";
			interrupts = <21>, <23>, <24>, <27>;
			interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
					  "emac_ptp_tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};
	};
};

&pruss1_mdio {
	status = "disabled";
	reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
	pruss1_eth0_phy: ethernet-phy@0 {
		reg = <0>;
		interrupt-parent = <&gpio3>;
		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
	};

	pruss1_eth1_phy: ethernet-phy@1 {
		reg = <1>;
		interrupt-parent = <&gpio3>;
		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
	};
};

&pruss2_eth {
	ti,pruss-gp-mux-sel = <4>,	/* MII2, needed for PRUSS1_MII0 */
			      <4>;	/* MII2, needed for PRUSS1_MII1 */
};

#include "am57xx-evm-cmem-am571x.dtsi"

I am also attaching dtb To dts converted file

7607.dtbTodts_converted_am571x-idk.txt

command used for dtb conversion is

make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- dtbs

Regards

Satheesh KumrS

0 satheesh kumar32 over 6 years ago in reply to satheesh kumar32

Expert 1045 points

Hello pavel

A gentle reminder

Regards

Satheesh Kumar S

0 Pavel Botev over 6 years ago in reply to satheesh kumar32

TI__Guru**** 170625 points

Satheesh,

I would suggest you to make direct registers read/writes in linux kernel. And once your project is ready with McASP, I2C and audio codec components, you can proceed with updating your DTS file.

You can make direct read/write of below registers in linux kernel with __raw_readl(reg) and __raw_writel(val, reg)

CM_COREAON_CLKOUTMUX2_CLKCTRL/0x4A0086B0

CM_CLKSEL_SYS_CLK1_CLKOUTMUX/0x4AE061C8

Before you write in this register, you need to convert this register address from physical to virtual. You can refer the below files for reference of __raw_writel usage:

linux-4.19.38/drivers/net/ethernet/ti/davinci_mdio.c

linux-4.19.38/sound/soc/ti/davinci-mcasp.c

You can add this code to below file and function:

linux-4.19.38/drivers/clk/ti/clk-7xx.c

dra7xx_dt_clk_init()

Regards,
Pavel

0 satheesh kumar32 over 5 years ago in reply to Pavel Botev

Expert 1045 points

Hello pavel

Sorry for delay response

Thanks for your support

I have modified the file

int __init dra7xx_dt_clk_init(void)
{
   int rc;
   volatile uint32_t* clkRegVirtulAddr1;
   volatile uint32_t* clkRegVirtulAddr2;
   struct clk *dpll_ck, *hdcp_ck;
   ti_dt_clocks_register(dra7xx_clks);

   omap2_clk_disable_autoidle_all();

   dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
   rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
   if (rc)
       pr_err("%s: failed to configure GMAC DPLL!\n", __func__);

   dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
   rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
   if (rc)
       pr_err("%s: failed to configure USB DPLL!\n", __func__);

   dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
   rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
   if (rc)
       pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);

   hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
   rc = clk_prepare_enable(hdcp_ck);
   if (rc)
       pr_err("%s: failed to set dss_deshdcp_clk\n", __func__);
   clkRegVirtulAddr1 =(volatile uint32_t*)ioremap(0x4A0086B0,4);
   (void)__raw_writel(0x00000100,clkRegVirtulAddr1);

   clkRegVirtulAddr2 =(volatile uint32_t*)ioremap(0x4AE061C8,4);
   (void)__raw_writel(0x00000001,clkRegVirtulAddr2);

   return rc;

}

With this code i can update 0x4AE061C8 only

No change 0x4A0086B0:0x00000000 .Is anythings more to be added?

Regards

Satheesh Kumar S

0 Pavel Botev over 5 years ago in reply to satheesh kumar32

TI__Guru**** 170625 points

Satheesh Kumar,

satheesh kumar32 said:
clkRegVirtulAddr1 =(volatile uint32_t*)ioremap(0x4A0086B0,4);
   (void)__raw_writel(0x00000100,clkRegVirtulAddr1);

   clkRegVirtulAddr2 =(volatile uint32_t*)ioremap(0x4AE061C8,4);
   (void)__raw_writel(0x00000001,clkRegVirtulAddr2);

I would suggest you to align to McASP driver:

linux-4.19.38/sound/soc/ti/davinci-mcasp.c

Thus you can use:

static void __iomem *reg1_base;

uint32_t value;

reg1_base = ioremap(0x4A0086B0,4); //CM_COREAON_CLKOUTMUX2_CLKCTRL

value = __raw_readl(reg1_base);

printk("default CM_COREAON_CLKOUTMUX2_CLKCTRL == %x \n",value);

__raw_writel(0x100,reg1_base);

value = __raw_readl(reg1_base);

printk("updated CM_COREAON_CLKOUTMUX2_CLKCTRL == %x \n",value);

Regards,
Pavel

0 satheesh kumar32 over 5 years ago in reply to Pavel Botev

Expert 1045 points

Hi Pavel

Thanks for your immediate support.

what do you mean by

I would suggest you to align to McASP driver:

linux-4.19.38/sound/soc/ti/davinci-mcasp.c

can I update the above modification on same place that I did earlier?

Regards

Satheesh Kumar S

0 Pavel Botev over 5 years ago in reply to satheesh kumar32

TI__Guru**** 170625 points

satheesh kumar32 said:
can I update the above modification on same place that I did earlier?

Yes

0 satheesh kumar32 over 5 years ago in reply to Pavel Botev

Expert 1045 points

Hi Pavel

Thanks

I have updated the file but no clock at clockout2 pin.But kernel log showing updated CM_COREAON_CLKOUTMUX2_CLKCTRL .

[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[ 0.000000] GIC: Using split EOI/Deactivate mode
[ 0.000000] default CM_COREAON_CLKOUTMUX2_CLKCTRL == 0
[ 0.000000] updated CM_COREAON_CLKOUTMUX2_CLKCTRL == 100
[ 0.000000] OMAP clockevent source: timer1 at 32786 Hz
[ 0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
[ 0.000005] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns.

Is their any issue with address translation?

Regards

Satheesh Kumar S

0 Pavel Botev over 5 years ago in reply to satheesh kumar32

TI__Guru**** 170625 points

Satheesh Kumar,

You should check (read) CM_COREAON_CLKOUTMUX2_CLKCTRL/0x4A0086B0 and CM_CLKSEL_SYS_CLK1_CLKOUTMUX/0x4AE061C8 values from user space with devmem2 tool. Thus you will be sure that kernel code writes to these registers successful.

Regards,
Pavel

0 satheesh kumar32 over 5 years ago in reply to Pavel Botev

Expert 1045 points

Hi Pavel

Thanks for your support

I have read the register using devmem2

root@am57xx-evm:~# devmem2 0x4a0086b0
/dev/mem opened.
Memory mapped at address 0xb6f1b000.
Read at address 0x4A0086B0 (0xb6f1b6b0): 0x00000000

root@am57xx-evm:~# devmem2 0x4ae061c8
/dev/mem opened.
Memory mapped at address 0xb6f78000.
Read at address 0x4AE061C8 (0xb6f781c8): 0x00000000

Regards

Satheesh Kumar S

0 Pavel Botev over 5 years ago in reply to satheesh kumar32

TI__Guru**** 170625 points

Satheesh Kumar,

Seems that these registers values has been overwritten from other kernel code or from rootfs init script. What I can suggest you is to trace your kernel boot flow and put this code (writing to registers) at the end of the kernel execution. If that does not work, you can update some of the init scripts in your rootfs.

Regards,
Pavel

0 satheesh kumar32 over 5 years ago in reply to Pavel Botev

Expert 1045 points

Hi Pavel

Thanks for your support

I am attaching the kernel log file

can you suggest the right place to update the register.

Just for curiosity,can you show init script from rootfs.

Fullscreen 7573.kernellog.txt Download

U-Boot SPL 2018.01-00569-gfd38f5afef-dirty (Aug 29 2019 - 11:59:09)
DRA722-GP ES2.0
Trying to boot from MMC1
no pinctrl state for default mode
no pinctrl state for default mode
Card did not respond to voltage select!
*** Warning - MMC init failed, using default environment



U-Boot 2018.01-00569-gfd38f5afef-dirty (Aug 29 2019 - 11:59:09 +0530)

CPU  : DRA722-GP ES2.0
Model: TI AM5718 IDK
Board: AM571x IDK REV 1.3B
DRAM:  1 GiB
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
Card did not respond to voltage select!
*** Warning - MMC init failed, using default environment

Card did not respond to voltage select!
invalid mmc device
SCSI:  SATA link 0 timeout.
AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst
scanning bus for devices...
Found 0 device(s).
Net:
Warning: ethernet@48484000 using MAC address from ROM
eth0: ethernet@48484000
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
** Unable to read file boot.scr **
1490 bytes read in 3 ms (484.4 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc0 ...
Running uenvcmd ...
1 bytes read in 1 ms (1000 Bytes/s)
Already setup.
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
4006400 bytes read in 190 ms (20.1 MiB/s)
97169 bytes read in 20 ms (4.6 MiB/s)
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
   Loading Device Tree to 8ffe5000, end 8ffffb90 ... OK

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.14.79-ge669d52447 (bcgl34@bcgl34-SVS15116GNB) (gcc version 4.8.3 20140401 (prerelease) (crosstool-NG linaro-1.13.1-4.8-2014.04 - Linaro GCC 4.8-2014.04)) #5 SMP PREEMPT Sat Sep 14 14:18:36 IST 2019
[    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
[    0.000000] CPU: div instructions available: patching division code
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[    0.000000] OF: fdt: Machine model: TI AM5718 IDK
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB
[    0.000000] OF: reserved mem: initialized node ipu2-memory@95800000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB
[    0.000000] OF: reserved mem: initialized node dsp1-memory@99000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB
[    0.000000] OF: reserved mem: initialized node ipu1-memory@9d000000, compatible id shared-dma-pool
[    0.000000] cma: Reserved 24 MiB at 0x00000000be400000
[    0.000000] OMAP4: Map 0x00000000bfd00000 to fe600000 for dram barrier
[    0.000000] DRA722 ES2.0
[    0.000000] percpu: Embedded 15 pages/cpu @ef649000 s31424 r8192 d21824 u61440
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 210496
[    0.000000] Kernel command line: console=ttyO2,115200n8 root=PARTUUID=f06a2576-02 rw rootfstype=ext4 rootwait
[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Memory: 644576K/848896K available (8192K kernel code, 348K rwdata, 2564K rodata, 2048K init, 283K bss, 24096K reserved, 180224K cma-reserved, 234496K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
[    0.000000]     vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0a00000   (10208 kB)
[    0.000000]       .init : 0xc0e00000 - 0xc1000000   (2048 kB)
[    0.000000]       .data : 0xc1000000 - 0xc1057100   ( 349 kB)
[    0.000000]        .bss : 0xc1059000 - 0xc109fdf0   ( 284 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  RCU restricting CPUs from NR_CPUS=2 to nr_cpu_ids=1.
[    0.000000]  Tasks RCU enabled.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] default CM_COREAON_CLKOUTMUX2_CLKCTRL == 0
[    0.000000] updated CM_COREAON_CLKOUTMUX2_CLKCTRL == 100
[    0.000000] default CM_COREAON_CLKOUTMUX2_CLKCTRL == 100
[    0.000000] updated CM_COREAON_CLKOUTMUX2_CLKCTRL == 100
[    0.000000] OMAP clockevent source: timer1 at 32786 Hz
[    0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
[    0.000005] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
[    0.000017] Switching to timer-based delay loop, resolution 162ns
[    0.000357] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
[    0.000366] OMAP clocksource: 32k_counter at 32768 Hz
[    0.000826] Console: colour dummy device 80x30
[    0.000844] WARNING: Your 'console=ttyO2' has been replaced by 'ttyS2'
[    0.000851] This ensures that you still see kernel messages. Please
[    0.000858] update your kernel commandline.
[    0.000878] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475)
[    0.000893] pid_max: default: 32768 minimum: 301
[    0.001011] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001024] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001555] CPU: Testing write buffer coherency: ok
[    0.001596] CPU0: Spectre v2: using ICIALLU workaround
[    0.001799] /cpus/cpu@0 missing clock-frequency property
[    0.001812] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.039848] Setting up static identity map for 0x80200000 - 0x80200060
[    0.059853] Hierarchical SRCU implementation.
[    0.080047] EFI services will not be available.
[    0.099913] smp: Bringing up secondary CPUs ...
[    0.099924] smp: Brought up 1 node, 1 CPU
[    0.099933] SMP: Total of 1 processors activated (12.29 BogoMIPS).
[    0.099941] CPU: All CPU(s) started in HYP mode.
[    0.099948] CPU: Virtualization extensions available.
[    0.100391] devtmpfs: initialized
[    0.118773] random: get_random_u32 called from bucket_table_alloc+0xfc/0x25c with crng_init=0
[    0.120056] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[    0.120258] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.120275] futex hash table entries: 256 (order: 2, 16384 bytes)
[    0.124313] pinctrl core: initialized pinctrl subsystem
[    0.124810] DMI not present or invalid.
[    0.125058] NET: Registered protocol family 16
[    0.130787] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.131655] omap_hwmod: l3_main_2 using broken dt data from ocp
[    0.325094] cpuidle: using governor ladder
[    0.325129] cpuidle: using governor menu
[    0.333423] OMAP GPIO hardware version 0.1
[    0.359175] No ATAGs?
[    0.359223] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
[    0.359236] hw-breakpoint: maximum watchpoint size is 8 bytes.
[    0.359625] omap4_sram_init:Unable to allocate sram needed to handle errata I688
[    0.359636] omap4_sram_init:Unable to get sram pool needed to handle errata I688
[    0.360167] OMAP DMA hardware revision 0.0
[    0.392360] edma 43300000.edma: memcpy is disabled
[    0.395676] edma 43300000.edma: TI EDMA DMA engine driver
[    0.402696] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver (LinkedList1/2/3 supported)
[    0.406214] omap-iommu 40d01000.mmu: 40d01000.mmu registered
[    0.406421] omap-iommu 40d02000.mmu: 40d02000.mmu registered
[    0.406662] omap-iommu 58882000.mmu: 58882000.mmu registered
[    0.406907] omap-iommu 55082000.mmu: 55082000.mmu registered
[    0.407215] iommu: Adding device 58820000.ipu to group 1
[    0.407299] iommu: Adding device 55020000.ipu to group 2
[    0.407446] iommu: Adding device 40800000.dsp to group 0
[    0.409975] palmas 0-0058: Irq flag is 0x00000004
[    0.432270] palmas 0-0058: Muxing GPIO 2f, PWM 0, LED 0
[    0.433919] SMPS12: supplied by regulator-dummy
[    0.435718] SMPS3: supplied by VMAIN
[    0.437333] SMPS45: supplied by regulator-dummy
[    0.439227] SMPS6: supplied by VMAIN
[    0.440955] SMPS7: supplied by VMAIN
[    0.442853] SMPS8: supplied by VMAIN
[    0.444155] SMPS9: supplied by VMAIN
[    0.445168] LDO1: supplied by VMAIN
[    0.451230] random: fast init done
[    0.451291] LDO2: supplied by VMAIN
[    0.461146] LDO3: supplied by VMAIN
[    0.471157] LDO4: supplied by VMAIN
[    0.481165] LDO5: supplied by regulator-dummy
[    0.481883] LDO6: supplied by regulator-dummy
[    0.482601] LDO7: supplied by regulator-dummy
[    0.483312] LDO8: supplied by regulator-dummy
[    0.484042] LDO9: supplied by VMAIN
[    0.491507] LDOLN: supplied by VMAIN
[    0.501213] LDOUSB: supplied by VMAIN
[    0.513963] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz
[    0.514176] media: Linux media interface: v0.10
[    0.514213] Linux video capture interface: v2.00
[    0.514295] pps_core: LinuxPPS API ver. 1 registered
[    0.514303] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.514322] PTP clock support registered
[    0.514350] EDAC MC: Ver: 3.0.0
[    0.520684] dmi: Firmware registration failed.
[    0.521114] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
[    0.521322] omap-mailbox 48842000.mailbox: omap mailbox rev 0x400
[    0.521678] Advanced Linux Sound Architecture Driver Initialized.
[    0.530752] clocksource: Switched to clocksource arch_sys_counter
[    0.538368] NET: Registered protocol family 2
[    0.538918] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[    0.538982] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[    0.539108] TCP: Hash tables configured (established 8192 bind 8192)
[    0.539178] UDP hash table entries: 512 (order: 2, 16384 bytes)
[    0.539211] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[    0.539329] NET: Registered protocol family 1
[    0.559689] RPC: Registered named UNIX socket transport module.
[    0.559700] RPC: Registered udp transport module.
[    0.559708] RPC: Registered tcp transport module.
[    0.559716] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.560621] hw perfevents: no interrupt-affinity property for /pmu, guessing.
[    0.560805] hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
[    0.561826] workingset: timestamp_bits=14 max_order=18 bucket_order=4
[    0.566121] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.576697] NFS: Registering the id_resolver key type
[    0.576723] Key type id_resolver registered
[    0.576731] Key type id_legacy registered
[    0.576769] ntfs: driver 2.1.32 [Flags: R/O].
[    0.578461] bounce: pool size: 64 pages
[    0.578507] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[    0.578517] io scheduler noop registered
[    0.578525] io scheduler deadline registered
[    0.578618] io scheduler cfq registered (default)
[    0.578627] io scheduler mq-deadline registered
[    0.578636] io scheduler kyber registered
[    0.583232] pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400 size 1128
[    0.583384] pinctrl-single 4a002e8c.pinmux: please update dts to use #pinctrl-cells = <1>
[    0.583455] pinctrl-single 4a002e8c.pinmux: initialized with no interrupts
[    0.583466] pinctrl-single 4a002e8c.pinmux: 1 pins at pa fc002e8c size 4
[    0.596248] dra7-pcie 51000000.pcie: Linked as a consumer to phy-4a094000.pciephy.1
[    0.596641] OF: PCI: host bridge /ocp/axi@0/pcie@51000000 ranges:
[    0.596677] OF: PCI:    IO 0x20003000..0x20012fff -> 0x00000000
[    0.596700] OF: PCI:   MEM 0x20013000..0x2fffffff -> 0x20013000
[    1.596964] dra7-pcie 51000000.pcie: phy link never came up
[    1.597101] dra7-pcie 51000000.pcie: PCI host bridge to bus 0000:00
[    1.597115] pci_bus 0000:00: root bus resource [bus 00-ff]
[    1.597127] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
[    1.597138] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
[    1.597456] PCI: bus0: Fast back to back transfers disabled
[    1.597545] PCI: bus1: Fast back to back transfers enabled
[    1.597582] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff 64bit]
[    1.597602] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[    1.597928] pcieport 0000:00:00.0: Signaling PME with IRQ 169
[    1.598058] pcieport 0000:00:00.0: AER enabled with IRQ 169
[    1.601124] V3_3D: supplied by smps9
[    1.601410] vtt_fixed: supplied by V3_3D
[    1.643971] Serial: 8250/16550 driver, 10 ports, IRQ sharing disabled
[    1.646770] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 45, base_baud = 3000000) is a 8250
[    2.716673] console [ttyS2] enabled
[    2.722121] omap_rng 48090000.rng: Random Number Generator ver. 20
[    2.729228] DSS: OMAP DSS rev 6.1
[    2.734287] omapdss_dss 58000000.dss: bound 58001000.dispc (ops dispc_component_ops)
[    2.742771] omapdss_dss 58000000.dss: bound 58040000.encoder (ops hdmi5_component_ops)
[    2.763427] brd: module loaded
[    2.772038] loop: module loaded
[    2.779245] m25p80 spi0.0: s25fl256s1 (32768 Kbytes)
[    2.784365] 7 ofpart partitions found on MTD device spi0.0
[    2.789876] Creating 7 MTD partitions on "spi0.0":
[    2.794733] 0x000000000000-0x000000040000 : "QSPI.SPL"
[    2.800598] 0x000000040000-0x000000140000 : "QSPI.u-boot"
[    2.806664] 0x000000140000-0x0000001c0000 : "QSPI.u-boot-spl-os"
[    2.813340] 0x0000001c0000-0x0000001d0000 : "QSPI.u-boot-env"
[    2.819744] 0x0000001d0000-0x0000001e0000 : "QSPI.u-boot-env.backup1"
[    2.826844] 0x0000001e0000-0x0000009e0000 : "QSPI.kernel"
[    2.832904] 0x0000009e0000-0x000002000000 : "QSPI.file-system"
[    2.839978] libphy: Fixed MDIO Bus: probed
[    2.900789] davinci_mdio 48485000.mdio: davinci mdio revision 1.6, bus freq 1000000
[    2.908483] davinci_mdio 48485000.mdio: detected phy mask fffffffc
[    2.929068] libphy: 48485000.mdio: probed
[    2.933154] davinci_mdio 48485000.mdio: phy[0]: device 48485000.mdio:00, driver Micrel KSZ9031 Gigabit PHY
[    2.942892] davinci_mdio 48485000.mdio: phy[1]: device 48485000.mdio:01, driver Micrel KSZ9031 Gigabit PHY
[    2.953465] cpsw 48484000.ethernet: Detected MACID = 44:ea:d8:14:14:02
[    2.960078] cpsw 48484000.ethernet: initialized cpsw ale version 1.4
[    2.966511] cpsw 48484000.ethernet: ALE Table size 1024
[    2.971806] cpsw 48484000.ethernet: device node lookup for pps timer failed
[    2.978831] cpsw 48484000.ethernet: cpts: overflow check period 500 (jiffies)
[    2.986738] cpsw 48484000.ethernet: cpsw: Detected MACID = 44:ea:d8:14:14:03
[    2.995002] i2c /dev entries driver
[    2.999235] IR NEC protocol handler initialized
[    3.003812] IR RC5(x/sz) protocol handler initialized
[    3.008886] IR RC6 protocol handler initialized
[    3.013448] IR JVC protocol handler initialized
[    3.017997] IR Sony protocol handler initialized
[    3.022917] IR SANYO protocol handler initialized
[    3.027640] IR Sharp protocol handler initialized
[    3.032378] IR MCE Keyboard/mouse protocol handler initialized
[    3.038235] IR XMP protocol handler initialized
[    3.048317] sdhci: Secure Digital Host Controller Interface driver
[    3.054629] sdhci: Copyright(c) Pierre Ossman
[    3.060100] sdhci-pltfm: SDHCI platform and OF driver helper
[    3.066522] sdhci-omap 4809c000.mmc: Got CD GPIO
[    3.071932] sdhci-omap 4809c000.mmc: no pinctrl state for ddr_1_8v mode
[    3.078575] sdhci-omap 4809c000.mmc: no pinctrl state for hs200_1_8v mode
[    3.140978] mmc0: SDHCI controller on 4809c000.mmc [4809c000.mmc] using ADMA
[    3.187903] mmc0: host does not support reading read-only switch, assuming write-enable
[    3.197919] mmc0: new high speed SDHC card at address 59b4
[    3.203820] mmcblk0: mmc0:59b4 USD   14.9 GiB
[    3.209755]  mmcblk0: p1 p2
[    3.212584] mmc1: SDHCI controller on 480b4000.mmc [480b4000.mmc] using ADMA
[    3.213630] ledtrig-cpu: registered to indicate activity on CPUs
[    3.223276] NET: Registered protocol family 10
[    3.234371] Segment Routing with IPv6
[    3.234408] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    3.234726] NET: Registered protocol family 17
[    3.234872] Key type dns_resolver registered
[    3.234955] omap_voltage_late_init: Voltage driver support not added
[    3.234958] Power Management for TI OMAP4+ devices.
[    3.235148] Registering SWP/SWPB emulation handler
[    3.279119] dmm 4e000000.dmm: workaround for errata i878 in use
[    3.289696] dmm 4e000000.dmm: initialized all PAT entries
[    3.296865] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    3.303655] [drm] No driver support for vblank timestamp query.
[    3.309722] [drm] Cannot find any crtc or sizes
[    3.318149] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
[    3.325693] hctosys: unable to open rtc device (rtc0)
[    3.331442] ALSA device list:
[    3.334420]   No soundcards found.
[    3.389986] ti-iodelay 4844a000.padconf: Set reg 0x18c Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.399156] ti-iodelay 4844a000.padconf: Set reg 0x1a4 Delay(a: 119 g: 0), Elements(C=0 F=3)0x29003
[    3.409270] ti-iodelay 4844a000.padconf: Set reg 0x1b0 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.419204] ti-iodelay 4844a000.padconf: Set reg 0x1bc Delay(a: 18 g: 0), Elements(C=0 F=0)0x29000
[    3.429213] ti-iodelay 4844a000.padconf: Set reg 0x1c8 Delay(a: 894 g: 0), Elements(C=1 F=11)0x2902b
[    3.439401] ti-iodelay 4844a000.padconf: Set reg 0x1d4 Delay(a: 30 g: 0), Elements(C=0 F=0)0x29000
[    3.449208] ti-iodelay 4844a000.padconf: Set reg 0x1e0 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.459044] ti-iodelay 4844a000.padconf: Set reg 0x1ec Delay(a: 23 g: 0), Elements(C=0 F=0)0x29000
[    3.468971] ti-iodelay 4844a000.padconf: Set reg 0x1f8 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.478769] ti-iodelay 4844a000.padconf: Set reg 0x360 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.488689] ti-iodelay 4844a000.padconf: Set reg 0x194 Delay(a: 152 g: 0), Elements(C=0 F=4)0x29004
[    3.498799] ti-iodelay 4844a000.padconf: Set reg 0x1ac Delay(a: 206 g: 0), Elements(C=0 F=5)0x29005
[    3.508896] ti-iodelay 4844a000.padconf: Set reg 0x1b8 Delay(a: 78 g: 0), Elements(C=0 F=2)0x29002
[    3.518852] ti-iodelay 4844a000.padconf: Set reg 0x1c4 Delay(a: 2 g: 0), Elements(C=0 F=0)0x29000
[    3.528724] ti-iodelay 4844a000.padconf: Set reg 0x1d0 Delay(a: 266 g: 0), Elements(C=0 F=7)0x29007
[    3.538748] ti-iodelay 4844a000.padconf: Set reg 0x1dc Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.548584] ti-iodelay 4844a000.padconf: Set reg 0x1e8 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.558767] ti-iodelay 4844a000.padconf: Set reg 0x1f4 Delay(a: 43 g: 0), Elements(C=0 F=1)0x29001
[    3.568650] ti-iodelay 4844a000.padconf: Set reg 0x200 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.578601] ti-iodelay 4844a000.padconf: Set reg 0x368 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.588344] ti-iodelay 4844a000.padconf: Set reg 0x190 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.598084] ti-iodelay 4844a000.padconf: Set reg 0x1a8 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.607824] ti-iodelay 4844a000.padconf: Set reg 0x1b4 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.617550] ti-iodelay 4844a000.padconf: Set reg 0x1c0 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.627312] ti-iodelay 4844a000.padconf: Set reg 0x1d8 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.637083] ti-iodelay 4844a000.padconf: Set reg 0x1e4 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.646820] ti-iodelay 4844a000.padconf: Set reg 0x1f0 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.656562] ti-iodelay 4844a000.padconf: Set reg 0x1fc Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.666203] ti-iodelay 4844a000.padconf: Set reg 0x364 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.677940] mmc1: new DDR MMC card at address 0001
[    3.684153] mmcblk1: mmc1:0001 R1J56L 13.8 GiB
[    3.688844] mmcblk1boot0: mmc1:0001 R1J56L partition 1 4.00 MiB
[    3.695290] mmcblk1boot1: mmc1:0001 R1J56L partition 2 4.00 MiB
[    3.702461] mmcblk1rpmb: mmc1:0001 R1J56L partition 3 128 KiB
[    3.710992]  mmcblk1: p1 p2
[    4.320822] [drm] Cannot find any crtc or sizes
[    5.360455] EXT4-fs (mmcblk0p2): recovery complete
[    5.370309] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
[    5.378591] VFS: Mounted root (ext4 filesystem) on device 179:2.
[    5.388897] devtmpfs: mounted
[    5.392989] Freeing unused kernel memory: 2048K
[    5.727502] systemd[1]: System time before build time, advancing clock.
[    5.773661] systemd[1]: systemd 234 running in system mode. (+PAM -AUDIT -SELINUX +IMA -APPARMOR +SMACK +SYSVINIT +UTMP -LIBCRYPTSETUP -GCRYPT -GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID -ELFUTILS +KMOD -IDN2 -IDN default-hierarchy=hybrid)
[    5.795331] systemd[1]: Detected architecture arm.

Welcome to Arago 2018.10!

[    5.832780] systemd[1]: Set hostname to <am57xx-evm>.
[    6.277890] random: systemd: uninitialized urandom read (16 bytes read)
[    6.286250] systemd[1]: Created slice System Slice.
[  OK  ] Created slice System Slice.
[    6.321065] random: systemd: uninitialized urandom read (16 bytes read)
[    6.330017] systemd[1]: Mounting POSIX Message Queue File System...
         Mounting POSIX Message Queue File System...
[    6.370901] random: systemd: uninitialized urandom read (16 bytes read)
[    6.377715] systemd[1]: Listening on udev Control Socket.
[  OK  ] Listening on udev Control Socket.
[    6.411614] systemd[1]: Listening on Journal Socket (/dev/log).
[  OK  ] Listening on Journal Socket (/dev/log).
[    6.440950] systemd[1]: Listening on udev Kernel Socket.
[  OK  ] Listening on udev Kernel Socket.
[    6.471115] systemd[1]: Reached target Remote File Systems.
[  OK  ] Reached target Remote File Systems.
[    6.502485] systemd[1]: Created slice system-serial\x2dgetty.slice.
[  OK  ] Created slice system-serial\x2dgetty.slice.
[  OK  ] Listening on Journal Socket.
[  OK  ] Listening on /dev/initctl Compatibility Named Pipe.
[  OK  ] Started Forward Password Requests to Wall Directory Watch.
[  OK  ] Started Dispatch Password Requests to Console Directory Watch.
[  OK  ] Reached target Paths.
[  OK  ] Listening on Syslog Socket.
         Starting Journal Service...
[  OK  ] Listening on Process Core Dump Socket.
         Starting Remount Root and Kernel File Systems...
[  OK  ] Reached target Swap.
[    6.835831] EXT4-fs (mmcblk0p2): re-mounted. Opts: (null)
[  OK  ] Listening on Network Service Netlink Socket.
[  OK  ] Created slice User and Session Slice.
[  OK  ] Reached target Slices.
         Mounting Temporary Directory (/tmp)...
         Starting Load Kernel Modules...
[    7.017411] cmemk: loading out-of-tree module taints kernel.
[  OK  ] Created slice system-getty.slice.
[    7.025948] CMEMK module: reference Linux version 4.14.79
[    7.036275] cmemk initialized
         Starting Create list of required st…ce nodes for the current k[    7.055939] cryptodev: driver 1.9 loaded.
ernel...
         Mounting Kernel Debug File System...
[    7.102028] usbcore: registered new interface driver usbfs
[    7.107584] usbcore: registered new interface driver hub
[    7.116400] usbcore: registered new device driver usb
[  OK  ] Mounted Kernel Debug File System.
[    7.133650] usbcore: registered new interface driver usbserial
[    7.150722] usbcore: registered new interface driver ftdi_sio
[[    7.157173] usbserial: USB Serial support registered for FTDI USB Serial Device
  OK  ] Mounted POSIX Message Queue File System.
[  OK  ] Mounted Temporary Directory (/tmp).
[  OK  ] Started Journal Service.
[  OK  ] Started Remount Root and Kernel File Systems.
[  OK  ] Started Load Kernel Modules.
[  OK  ] Started Create list of required sta…vice nodes for the current kernel.
         Mounting Kernel Configuration File System...
         Starting Apply Kernel Variables...
         Starting Create System Users...
         Starting Rebuild Hardware Database...
         Starting Flush Journal to Persistent Storage...
[  OK  ] Mounted Kernel Configuration File System.
[  OK  ] Started Apply Kernel Variables.
[  OK  ] Started Create System Users.
[    7.595822] systemd-journald[75]: Received request to flush runtime journal from PID 1
         Starting Create Static Device Nodes in /dev...
[  OK  ] Started Flush Journal to Persistent Storage.
[  OK  ] Started Create Static Device Nodes in /dev.
[  OK  ] Reached target Local File Systems (Pre).
         Mounting /media/ram...
         Mounting /var/volatile...
         Starting udev Kernel Device Manager...
[  OK  ] Mounted /var/volatile.
[  OK  ] Mounted /media/ram.
         Starting Load/Save Random Seed...
[  OK  ] Reached target Local File Systems.
         Starting Rebuild Dynamic Linker Cache...
         Starting Create Volatile Files and Directories...
         Starting Rebuild Journal Catalog...
[  OK  ] Started Load/Save Random Seed.
[  OK  ] Started Create Volatile Files and Directories.
[  OK  ] Started Rebuild Journal Catalog.
[  OK  ] Started udev Kernel Device Manager.
         Starting Update UTMP about System Boot/Shutdown...
         Starting Network Time Synchronization...
[  OK  ] Started Update UTMP about System Boot/Shutdown.
[  OK  ] Started Rebuild Dynamic Linker Cache.
[  OK  ] Started Network Time Synchronization.
[  OK  ] Reached target System Time Synchronized.
[  OK  ] Started Rebuild Hardware Database.
         Starting Update is Completed...
         Starting udev Coldplug all Devices...
[  OK  ] Started Update is Completed.
[  OK  ] Started udev Coldplug all Devices.
[  OK  ] Reached target System Initialization.
[  OK  ] Listening on dropbear.socket.
[  OK  ] Started Daily rotation of log files.
[  OK  ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket.
[  OK  ] Started Daily Cleanup of Temporary Directories.
[  OK  ] Reached target Timers.
[  OK  ] Listening on RPCbind Server Activation Socket.
         Starting Network Service...
[  OK  ] Listening on D-Bus System Message Bus Socket.
[  OK  ] Reached target Sockets.
[   11.708219] omap-rproc 58820000.ipu: assigned reserved memory node ipu1-memory@9d000000
[  OK  ] Reached target Basic System.
[   11.766795] remoteproc remoteproc0: 58820000.ipu is available
[  OK  ] Started D-Bus System Message Bus.
[   11.832272] omap-rproc 55020000.ipu: assigned reserved memory node ipu2-memory@95800000
[   11.939292] remoteproc remoteproc1: 55020000.ipu is available
[   11.974243] omap-rproc 40800000.dsp: assigned reserved memory node dsp1-memory@99000000
[   12.000414] remoteproc remoteproc2: 40800000.dsp is available
[   12.070108] omap_gpio 4805b000.gpio: Could not set line 7 debounce to 20000 microseconds (-22)
[   12.081037] ov2659 0-0030: Sensor detection failed (3030, 0)
[   12.198026] remoteproc remoteproc0: powering up 58820000.ipu
[   12.208063] remoteproc remoteproc0: Booting fw image dra7-ipu1-fw.xem4, size 6731716
[   12.243961] omap-iommu 58882000.mmu: 58882000.mmu: version 2.1
[   12.255638] palmas-rtc 48070000.i2c:tps659038@58:tps659038_rtc: rtc core: registered 48070000.i2c:tps659038@58:tps659038_rtc as rtc0
[   12.335635] virtio_rpmsg_bus virtio0: rpmsg host is online
[   12.344741] remoteproc remoteproc0: registered virtio0 (type 7)
[   12.382239] remoteproc remoteproc0: remote processor 58820000.ipu is now up
[   12.408165] remoteproc remoteproc1: powering up 55020000.ipu
[   12.414316] remoteproc remoteproc1: Booting fw image dra7-ipu2-fw.xem4, size 3747220
[   12.432653] omap-iommu 55082000.mmu: 55082000.mmu: version 2.1
[   12.456734] omap-des 480a5000.des: OMAP DES hw accel rev: 2.2
[   12.482102] omap-des 480a5000.des: will run requests pump with realtime priority
[   12.505748] virtio_rpmsg_bus virtio0: creating channel rpmsg-proto addr 0x3d
[   12.544931] omap_rtc 48838000.rtc: registered as rtc1
[   12.618881] virtio_rpmsg_bus virtio1: rpmsg host is online
[   12.643596] remoteproc remoteproc1: registered virtio1 (type 7)
[   12.659929] remoteproc remoteproc1: remote processor 55020000.ipu is now up
[   12.675198] virtio_rpmsg_bus virtio1: creating channel rpmsg-rpc addr 0x65
[   12.700965] virtio_rpmsg_bus virtio1: creating channel rpmsg-rpc addr 0x66
[   13.525808] remoteproc remoteproc2: powering up 40800000.dsp
[   13.537032] vpe 489d0000.vpe: loading firmware vpdma-1b8.bin
[   13.602232] remoteproc remoteproc2: Booting fw image dra7-dsp1-fw.xe66, size 20430464
[   13.676103] SCSI subsystem initialized
[   13.703987] vip 48970000.vip: loading firmware vpdma-1b8.bin
[   13.757667] ahci 4a140000.sata: SSS flag set, parallel bus scan disabled
[   13.757687] ahci 4a140000.sata: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl platform mode
[   13.757693] ahci 4a140000.sata: flags: 64bit ncq sntf stag pm led clo only pmp pio slum part ccc apst
[  OK  ] Started Job spooling tools.
[   13.926450] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
[   13.932342] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
[   13.938302] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0
[  OK  ] Started Kernel Logging Service.
[  OK  ] Started System Logging Service.
         Starting Print notice about GPLv3 packages...
[  OK  ] Started Periodic Command Scheduler.
         Starting TI MultiCore Tools Daemon...
         Starting uim-sysfs.service...
         Starting Login Service...
         Starting RPC Bind Service...
         Starting TI IPC Daemon...
[  OK  ] Reached target Containers.
[  OK  ] Started Hardware RNG Entropy Gatherer Daemon.
[   14.332071] net eth1: initializing cpsw version 1.15 (0)
[   14.370814] vip 48970000.vip: VPDMA firmware loaded
[   14.371127] vpe 489d0000.vpe: Device registered as /dev/video0
[   14.386580] scsi host0: ahci
[   14.386773] ata1: SATA max UDMA/133 mmio [mem 0x4a140000-0x4a1410ff] port 0x100 irq 80
[   14.387823] omap_wdt: OMAP Watchdog Timer Rev 0x01: initial timeout 60 sec
[   14.460900] random: crng init done
[   14.460905] random: 7 urandom warning(s) missed due to ratelimiting
[   14.491215] omap-sham 4b101000.sham: hw accel on OMAP rev 4.3
[   14.521157] virtio_rpmsg_bus virtio2: rpmsg host is online
[   14.521220] remoteproc remoteproc2: registered virtio2 (type 7)
[   14.521225] remoteproc remoteproc2: remote processor 40800000.dsp is now up
[   14.570740] virtio_rpmsg_bus virtio2: creating channel rpmsg-proto addr 0x3d
[   14.639523] omap-aes 4b500000.aes: OMAP AES hw accel rev: 3.3
[   14.655386] omap-aes 4b500000.aes: will run requests pump with realtime priority
[   14.688809] omap-aes 4b700000.aes: OMAP AES hw accel rev: 3.3
[   14.693268] omap-aes 4b700000.aes: will run requests pump with realtime priority
[   14.726479] ata1: SATA link down (SStatus 0 SControl 300)
[   14.914453] [drm] Initialized pvr 1.14.3699939 20110701 for 56000000.gpu on minor 1
[   15.068980] FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
[   15.441610] omap-hdmi-audio omap-hdmi-audio.0.auto: snd-soc-dummy-dai <-> 58040000.encoder mapping ok
[   15.441617] omap-hdmi-audio omap-hdmi-audio.0.auto: ASoC: no DMI vendor name!
         Starting Avahi mDNS/DNS-SD Stack...
[  OK  ] Started Network Service.
[  OK  ] Started TI MultiCore Tools Daemon.
[  OK  ] Started RPC Bind Service.
[  OK  ] Started TI IPC Daemon.
[  OK  ] Found device /dev/ttyS2.
[   16.146935] Micrel KSZ9031 Gigabit PHY 48485000.mdio:01: attached PHY driver [Micrel KSZ9031 Gigabit PHY] (mii_bus:phy_addr=48485000.mdio:01, irq=POLL)
[   16.368660] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
[   16.561057] CAN device driver interface
[   16.576449] net eth0: initializing cpsw version 1.15 (0)
[   16.821398] Micrel KSZ9031 Gigabit PHY 48485000.mdio:00: attached PHY driver [Micrel KSZ9031 Gigabit PHY] (mii_bus:phy_addr=48485000.mdio:00, irq=POLL)
[   17.025739] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[   17.085141] c_can_platform 4ae3c000.can: c_can_platform device registered (regs=fce3c000, irq=88)
[  OK  ] Started Avahi mDNS/DNS-SD Stack.
[  OK  ] Started Login Service.
[  OK  ] Listening on Load/Save RF Kill Switch Status /dev/rfkill Watch.
         Starting Wait for Network to be Configured...
[  OK  ] Reached target Network.
         Starting Simple Network Management Protocol (SNMP) Daemon....
[  OK  ] Started Redis In-Memory Data Store.
         Starting Permit User Sessions...
         Starting Lightning Fast Webserver With Light System Requirements...
         Starting Enable and configure wl18xx bluetooth stack...
         Starting Network Name Resolution...
[  OK  ] Started Permit User Sessions.
[  OK  ] Started Getty on tty1.
[  OK  ] Started Serial Getty on ttyS2.
[  OK  ] Reached target Login Prompts.
         Starting Synchronize System and HW clocks...
[  OK  ] Started uim-sysfs.service.
[  OK  ] Started Enable and configure wl18xx bluetooth stack.
[  OK  ] Started Synchronize System and HW clocks.
[  OK  ] Started Lightning Fast Webserver With Light System Requirements.
[  OK  ] Started Network Name Resolution.
[   18.786014] NET: Registered protocol family 44
[   18.798423] rpmsg_rpc virtio1.rpmsg-rpc.-1.101: probing service dce-callback with src 1024 dst 101
[   18.799228] rpmsg_rpc virtio1.rpmsg-rpc.-1.101: published functions = 4
[   18.799676] rpmsg_rpc virtio1.rpmsg-rpc.-1.102: probing service rpmsg-dce with src 1025 dst 102
[   18.800237] rpmsg_rpc virtio1.rpmsg-rpc.-1.102: published functions = 9
[  OK  ] Started Simple Network Management Protocol (SNMP) Daemon..
[   19.025477] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[   19.054845] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 1
[   19.090506] xhci-hcd xhci-hcd.1.auto: hcc params 0x0220f04c hci version 0x100 quirks 0x02010010
[   19.114372] xhci-hcd xhci-hcd.1.auto: irq 176, io mem 0x48890000
[   19.131922] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[   19.150251] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[   19.169773] usb usb1: Product: xHCI Host Controller
[   19.183556] usb usb1: Manufacturer: Linux 4.14.79-ge669d52447 xhci-hcd
[   19.200818] usb usb1: SerialNumber: xhci-hcd.1.auto
[   19.218060] hub 1-0:1.0: USB hub found
[   19.229943] hub 1-0:1.0: 1 port detected
[   19.244715] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[   19.260058] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 2
[   19.281335] xhci-hcd xhci-hcd.1.auto: Host supports USB 3.0  SuperSpeed
[   19.298822] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[   19.321855] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
[   19.340286] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[   19.359725] usb usb2: Product: xHCI Host Controller
[   19.373548] usb usb2: Manufacturer: Linux 4.14.79-ge669d52447 xhci-hcd
[   19.390799] usb usb2: SerialNumber: xhci-hcd.1.auto
[   19.406135] hub 2-0:1.0: USB hub found
[   19.418152] hub 2-0:1.0: 1 port detected
[  OK  ] Reached target Sound Card.
[  OK  ] Reached target Host and Network Name Lookups.
[  OK  ] Started NFS status monitor for NFSv2/3 locking..
         Starting rc.pvr.service...
[   20.501971] PVR_K: UM DDK-(3699939) and KM DDK-(3699939) match. [ OK ]
[  OK  ] Started rc.pvr.service.
         Starting weston.service...
***************************************************************
***************************************************************
NOTICE: This file system contains the following GPLv3 packages:
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        bash
        binutils-dev
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        libgdbm4
        libgettextlib
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        mavros
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        socketcan-interface
        swig-dev
        swig
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If you do not wish to distribute GPLv3 components please remove
the above packages prior to distribution.  This can be done using
the opkg remove command.  i.e.:
    opkg remove <package>
Where <package> is the name printed in the list above

NOTE: If the package is a dependency of another package you
      will be notified of the dependent packages.  You should
      use the --force-removal-of-dependent-packages option to
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***************************************************************
***************************************************************
[  OK  ] Started Print notice about GPLv3 packages.

 _____                    _____           _         _
|  _  |___ ___ ___ ___   |  _  |___ ___  |_|___ ___| |_
|     |  _| .'| . | . |  |   __|  _| . | | | -_|  _|  _|
|__|__|_| |__,|_  |___|  |__|  |_| |___|_| |___|___|_|
              |___|                    |___|

Arago Project http://arago-project.org am57xx-evm ttyS2

Arago 2018.10 am57xx-evm ttyS2

am57xx-evm login: [   25.448321] omap_hwmod: mmu0_dsp1: _wait_target_disable failed

Regards

satheesh Kumar S

0 Pavel Botev over 5 years ago in reply to satheesh kumar32

TI__Guru**** 170625 points

satheesh Kumar S,

I try this on my side, I am using AM572x IDK with PSDK Linux v6.00. I am using the default (pre-biult) DTB file am572x-idk.dtb and I make modifications only to linux kernel, thus updating only zImage file.

First I updated clk-7xx.c file as we discussed, and I see later in user space that only CM_CLKSEL_SYS_CLK1_CLKOUTMUX/0x4AE061C8 value is correct, while CM_COREAON_CLKOUTMUX2_CLKCTRL/0x4A0086B0 has been overwritten to 0x0. Then I made similar update to below file, but only for CM_COREAON_CLKOUTMUX2_CLKCTRL, as other register CM_CLKSEL_SYS_CLK1_CLKOUTMUX already have the value we need in user space.

linux-4.19.38/sound/last.c

I am attaching for your reference:

- full console log, boot up + devmem2

Fullscreen clkout2_log.txt Download

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.19.38-g4dae378bbe (pbotev@lin-0306) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #2 SMP PREEMPT Mon Sep 16 16:06:25 EEST 2019
[    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
[    0.000000] CPU: div instructions available: patching division code
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[    0.000000] OF: fdt: Machine model: TI AM5728 IDK
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB
[    0.000000] OF: reserved mem: initialized node ipu2-memory@95800000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB
[    0.000000] OF: reserved mem: initialized node dsp1-memory@99000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB
[    0.000000] OF: reserved mem: initialized node ipu1-memory@9d000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x000000009f000000, size 8 MiB
[    0.000000] OF: reserved mem: initialized node dsp2-memory@9f000000, compatible id shared-dma-pool
[    0.000000] cma: Reserved 24 MiB at 0x00000000fe400000
[    0.000000] OMAP4: Map 0x00000000ffd00000 to (ptrval) for dram barrier
[    0.000000] DRA752 ES2.0
[    0.000000] random: get_random_bytes called from start_kernel+0xb4/0x470 with crng_init=0
[    0.000000] percpu: Embedded 15 pages/cpu s32396 r8192 d20852 u61440
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 472640
[    0.000000] Kernel command line: console=ttyO2,115200n8 root=PARTUUID=4ec5d63c-02 rw rootfstype=ext4 rootwait
[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Memory: 1675788K/1897472K available (8192K kernel code, 321K rwdata, 2672K rodata, 2048K init, 267K bss, 33268K reserved, 188416K cma-reserved, 1283072K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
[    0.000000]     vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0x(ptrval) - 0x(ptrval)   (10208 kB)
[    0.000000]       .init : 0x(ptrval) - 0x(ptrval)   (2048 kB)
[    0.000000]       .data : 0x(ptrval) - 0x(ptrval)   ( 322 kB)
[    0.000000]        .bss : 0x(ptrval) - 0x(ptrval)   ( 268 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] 	Tasks RCU enabled.
[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] dra7xx_dt_clk_init() -> register write
[    0.000000] default CM_COREAON_CLKOUTMUX2_CLKCTRL == 0 
[    0.000000] updated CM_COREAON_CLKOUTMUX2_CLKCTRL == 100 
[    0.000000] default CM_CLKSEL_SYS_CLK1_CLKOUTMUX == 0 
[    0.000000] updated CM_CLKSEL_SYS_CLK1_CLKOUTMUX == 1 
[    0.000000] OMAP clockevent source: timer1 at 32786 Hz
[    0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
[    0.000005] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
[    0.000018] Switching to timer-based delay loop, resolution 162ns
[    0.000293] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
[    0.000303] OMAP clocksource: 32k_counter at 32768 Hz
[    0.000758] Console: colour dummy device 80x30
[    0.000778] WARNING: Your 'console=ttyO2' has been replaced by 'ttyS2'
[    0.000786] This ensures that you still see kernel messages. Please
[    0.000794] update your kernel commandline.
[    0.000829] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475)
[    0.000846] pid_max: default: 32768 minimum: 301
[    0.000967] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.000981] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001534] CPU: Testing write buffer coherency: ok
[    0.001574] CPU0: Spectre v2: using ICIALLU workaround
[    0.001786] /cpus/cpu@0 missing clock-frequency property
[    0.001806] /cpus/cpu@1 missing clock-frequency property
[    0.001819] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.059923] Setting up static identity map for 0x80200000 - 0x80200060
[    0.079936] rcu: Hierarchical SRCU implementation.
[    0.100124] EFI services will not be available.
[    0.119995] smp: Bringing up secondary CPUs ...
[    0.200379] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.200385] CPU1: Spectre v2: using ICIALLU workaround
[    0.200508] smp: Brought up 1 node, 2 CPUs
[    0.200521] SMP: Total of 2 processors activated (24.59 BogoMIPS).
[    0.200530] CPU: All CPU(s) started in HYP mode.
[    0.200537] CPU: Virtualization extensions available.
[    0.201091] devtmpfs: initialized
[    0.217954] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[    0.218210] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.218228] futex hash table entries: 512 (order: 3, 32768 bytes)
[    0.221342] pinctrl core: initialized pinctrl subsystem
[    0.221858] DMI not present or invalid.
[    0.222134] NET: Registered protocol family 16
[    0.223254] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.224184] omap_hwmod: l3_main_2 using broken dt data from ocp
[    0.421638] cpuidle: using governor ladder
[    0.421673] cpuidle: using governor menu
[    0.432030] OMAP GPIO hardware version 0.1
[    0.456639] No ATAGs?
[    0.456713] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
[    0.456729] hw-breakpoint: maximum watchpoint size is 8 bytes.
[    0.457251] omap4_sram_init:Unable to allocate sram needed to handle errata I688
[    0.457263] omap4_sram_init:Unable to get sram pool needed to handle errata I688
[    0.457892] OMAP DMA hardware revision 0.0
[    0.468583] edma 43300000.edma: memcpy is disabled
[    0.471977] edma 43300000.edma: TI EDMA DMA engine driver
[    0.478991] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver (LinkedList1/2/3 supported)
[    0.482515] omap-iommu 40d01000.mmu: 40d01000.mmu registered
[    0.482699] omap-iommu 40d02000.mmu: 40d02000.mmu registered
[    0.482945] omap-iommu 58882000.mmu: 58882000.mmu registered
[    0.483182] omap-iommu 55082000.mmu: 55082000.mmu registered
[    0.483550] omap-iommu 41501000.mmu: 41501000.mmu registered
[    0.483733] omap-iommu 41502000.mmu: 41502000.mmu registered
[    0.484004] iommu: Adding device 58820000.ipu to group 1
[    0.484083] iommu: Adding device 55020000.ipu to group 2
[    0.484207] iommu: Adding device 40800000.dsp to group 0
[    0.484443] iommu: Adding device 41000000.dsp to group 3
[    0.486478] palmas 0-0058: Irq flag is 0x00000004
[    0.512048] palmas 0-0058: Muxing GPIO 2d, PWM 0, LED 0
[    0.513755] SMPS12: supplied by regulator-dummy
[    0.515475] SMPS3: supplied by VMAIN
[    0.517062] SMPS45: supplied by regulator-dummy
[    0.518929] SMPS6: supplied by VMAIN
[    0.520637] SMPS7: supplied by VMAIN
[    0.522508] SMPS8: supplied by VMAIN
[    0.523778] SMPS9: supplied by VMAIN
[    0.524730] LDO1: supplied by VMAIN
[    0.531341] LDO2: supplied by VMAIN
[    0.531398] random: fast init done
[    0.541208] LDO3: supplied by VMAIN
[    0.551215] LDO4: supplied by VMAIN
[    0.561240] LDO5: supplied by regulator-dummy
[    0.561937] LDO6: supplied by regulator-dummy
[    0.562629] LDO7: supplied by regulator-dummy
[    0.563315] LDO8: supplied by regulator-dummy
[    0.564000] LDO9: supplied by VMAIN
[    0.571566] LDOLN: supplied by VMAIN
[    0.581270] LDOUSB: supplied by VMAIN
[    0.593934] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz
[    0.594145] media: Linux media interface: v0.10
[    0.594184] videodev: Linux video capture interface: v2.00
[    0.594256] pps_core: LinuxPPS API ver. 1 registered
[    0.594266] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.594287] PTP clock support registered
[    0.594317] EDAC MC: Ver: 3.0.0
[    0.601181] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
[    0.601430] omap-mailbox 48842000.mailbox: omap mailbox rev 0x400
[    0.601791] Advanced Linux Sound Architecture Driver Initialized.
[    0.602566] clocksource: Switched to clocksource arch_sys_counter
[    0.610437] NET: Registered protocol family 2
[    0.611047] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes)
[    0.611076] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[    0.611140] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[    0.611267] TCP: Hash tables configured (established 8192 bind 8192)
[    0.611336] UDP hash table entries: 512 (order: 2, 16384 bytes)
[    0.611370] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[    0.611503] NET: Registered protocol family 1
[    0.611926] RPC: Registered named UNIX socket transport module.
[    0.611937] RPC: Registered udp transport module.
[    0.611946] RPC: Registered tcp transport module.
[    0.611955] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.612996] hw perfevents: no interrupt-affinity property for /pmu, guessing.
[    0.613171] hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
[    0.614119] Initialise system trusted keyrings
[    0.614252] workingset: timestamp_bits=14 max_order=19 bucket_order=5
[    0.619025] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.619481] NFS: Registering the id_resolver key type
[    0.619507] Key type id_resolver registered
[    0.619516] Key type id_legacy registered
[    0.619555] ntfs: driver 2.1.32 [Flags: R/O].
[    0.619884] pstore: using deflate compression
[    0.621224] Key type asymmetric registered
[    0.621237] Asymmetric key parser 'x509' registered
[    0.621285] bounce: pool size: 64 pages
[    0.621325] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[    0.621336] io scheduler noop registered
[    0.621346] io scheduler deadline registered
[    0.621444] io scheduler cfq registered (default)
[    0.621454] io scheduler mq-deadline registered
[    0.621464] io scheduler kyber registered
[    0.626714] pinctrl-single 4a003400.pinmux: 282 pins, size 1128
[    0.629532] dra7-pcie 51000000.pcie: Linked as a consumer to phy-4a094000.pciephy.1
[    0.629795] dra7-pcie 51000000.pcie: WA for Errata i870 not applied
[    0.629889] dra7-pcie 51000000.pcie: host bridge /ocp/axi@0/pcie@51000000 ranges:
[    0.629932] dra7-pcie 51000000.pcie:    IO 0x20003000..0x20012fff -> 0x00000000
[    0.629959] dra7-pcie 51000000.pcie:   MEM 0x20013000..0x2fffffff -> 0x20013000
[    1.630246] dra7-pcie 51000000.pcie: Phy link never came up
[    1.630379] dra7-pcie 51000000.pcie: PCI host bridge to bus 0000:00
[    1.630394] pci_bus 0000:00: root bus resource [bus 00-ff]
[    1.630405] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
[    1.630417] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
[    1.636404] PCI: bus0: Fast back to back transfers disabled
[    1.641896] PCI: bus1: Fast back to back transfers enabled
[    1.641938] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff 64bit]
[    1.641958] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[    1.642268] pcieport 0000:00:00.0: Signaling PME with IRQ 172
[    1.642397] pcieport 0000:00:00.0: AER enabled with IRQ 172
[    1.646039] V3_3D: supplied by smps9
[    1.646299] vtt_fixed: supplied by V3_3D
[    1.690212] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled
[    1.693764] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 45, base_baud = 3000000) is a 8250
[    2.806704] console [ttyS2] enabled
[    2.812386] omap_rng 48090000.rng: Random Number Generator ver. 20
[    2.819415] omapdss_dss 58000000.dss: Linked as a consumer to regulator.20
[    2.826491] DSS: OMAP DSS rev 6.1
[    2.832714] omapdss_hdmi5 58040000.encoder: Linked as a consumer to regulator.13
[    2.840221] omapdss_hdmi5 58040000.encoder: Dropping the link to regulator.13
[    2.860237] brd: module loaded
[    2.869372] loop: module loaded
[    2.877078] m25p80 spi0.0: s25fl256s1 (32768 Kbytes)
[    2.882133] 7 fixed-partitions partitions found on MTD device spi0.0
[    2.888576] Creating 7 MTD partitions on "spi0.0":
[    2.893417] 0x000000000000-0x000000040000 : "QSPI.SPL"
[    2.899286] 0x000000040000-0x000000140000 : "QSPI.u-boot"
[    2.905412] 0x000000140000-0x0000001c0000 : "QSPI.u-boot-spl-os"
[    2.912092] 0x0000001c0000-0x0000001d0000 : "QSPI.u-boot-env"
[    2.918536] 0x0000001d0000-0x0000001e0000 : "QSPI.u-boot-env.backup1"
[    2.925678] 0x0000001e0000-0x0000009e0000 : "QSPI.kernel"
[    2.931747] 0x0000009e0000-0x000002000000 : "QSPI.file-system"
[    2.938880] libphy: Fixed MDIO Bus: probed
[    3.002604] davinci_mdio 48485000.mdio: davinci mdio revision 1.6, bus freq 1000000
[    3.010301] davinci_mdio 48485000.mdio: detected phy mask fffffffc
[    3.020916] libphy: 48485000.mdio: probed
[    3.024982] davinci_mdio 48485000.mdio: phy[0]: device 48485000.mdio:00, driver Micrel KSZ9031 Gigabit PHY
[    3.034720] davinci_mdio 48485000.mdio: phy[1]: device 48485000.mdio:01, driver Micrel KSZ9031 Gigabit PHY
[    3.045128] cpsw 48484000.ethernet: Detected MACID = 7c:38:66:7e:d2:1e
[    3.051727] cpsw 48484000.ethernet: initialized cpsw ale version 1.4
[    3.058147] cpsw 48484000.ethernet: ALE Table size 1024
[    3.063465] cpsw 48484000.ethernet: cpts: overflow check period 500 (jiffies)
[    3.071426] cpsw 48484000.ethernet: cpsw: Detected MACID = 7c:38:66:7e:d2:1f
[    3.079749] i2c /dev entries driver
[    3.088206] cpu cpu0: Linked as a consumer to regulator.4
[    3.093739] cpu cpu0: Linked as a consumer to regulator.27
[    3.100842] sdhci: Secure Digital Host Controller Interface driver
[    3.107101] sdhci: Copyright(c) Pierre Ossman
[    3.112639] sdhci-pltfm: SDHCI platform and OF driver helper
[    3.119098] omap_gpio 4805d000.gpio: Could not set line 27 debounce to 200000 microseconds (-22)
[    3.128174] sdhci-omap 4809c000.mmc: Got CD GPIO
[    3.132988] sdhci-omap 4809c000.mmc: Linked as a consumer to regulator.26
[    3.140023] sdhci-omap 4809c000.mmc: Linked as a consumer to regulator.11
[    3.146904] sdhci-omap 4809c000.mmc: Dropping the link to regulator.11
[    3.153539] sdhci-omap 4809c000.mmc: Linked as a consumer to regulator.2
[    3.160458] sdhci-omap 4809c000.mmc: Linked as a consumer to regulator.11
[    3.167354] sdhci-omap 4809c000.mmc: no pinctrl state for ddr_3_3v mode
[    3.200751] mmc0: SDHCI controller on 4809c000.mmc [4809c000.mmc] using ADMA
[    3.208850] sdhci-omap 480b4000.mmc: Linked as a consumer to regulator.2
[    3.215684] sdhci-omap 480b4000.mmc: Dropping the link to regulator.2
[    3.222412] sdhci-omap 480b4000.mmc: Linked as a consumer to regulator.2
[    3.255440] mmc1: SDHCI controller on 480b4000.mmc [480b4000.mmc] using ADMA
[    3.263983] ledtrig-cpu: registered to indicate activity on CPUs
[    3.271875] mmc0: host does not support reading read-only switch, assuming write-enable
[    3.281458] NET: Registered protocol family 10
[    3.281915] mmc0: new high speed SDHC card at address 1388
[    3.302066] Segment Routing with IPv6
[    3.302212] mmcblk0: mmc0:1388 USD00 29.5 GiB 
[    3.305867] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    3.316669] NET: Registered protocol family 17
[    3.321346] Key type dns_resolver registered
[    3.324426]  mmcblk0: p1 p2
[    3.325806] Registering SWP/SWPB emulation handler
[    3.333288] omap_voltage_late_init: Voltage driver support not added
[    3.339690] Power Management for TI OMAP4+ devices.
[    3.345133] Loading compiled-in X.509 certificates
[    3.361996] mmc1: new DDR MMC card at address 0001
[    3.372477] dmm 4e000000.dmm: workaround for errata i878 in use
[    3.377513] mmcblk1: mmc1:0001 R1J56L 13.8 GiB 
[    3.379871] dmm 4e000000.dmm: initialized all PAT entries
[    3.383377] mmcblk1boot0: mmc1:0001 R1J56L partition 1 4.00 MiB
[    3.394769] omapdss_hdmi5 58040000.encoder: Linked as a consumer to regulator.13
[    3.394803] mmcblk1boot1: mmc1:0001 R1J56L partition 2 4.00 MiB
[    3.402272] omapdss_hdmi5 58040000.encoder: Dropping the link to regulator.13
[    3.415477] mmcblk1rpmb: mmc1:0001 R1J56L partition 3 128 KiB, chardev (244:0)
[    3.423648] omapdss_hdmi5 58040000.encoder: Linked as a consumer to regulator.13
[    3.431463] omapdss_dss 58000000.dss: bound 58001000.dispc (ops dispc_component_ops)
[    3.439548] omapdss_dss 58000000.dss: bound 58040000.encoder (ops hdmi5_component_ops)
[    3.448292] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    3.454959] [drm] No driver support for vblank timestamp query.
[    3.460920] [drm] Cannot find any crtc or sizes
[    3.466171] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
[    3.473756] hctosys: unable to open rtc device (rtc0)
[    3.479542] ALSA device list:
[    3.482519]   No soundcards found.
[    3.485969] alsa_sound_last_init() -> register write
[    3.490956] default CM_COREAON_CLKOUTMUX2_CLKCTRL == 0 
[    3.496238] updated CM_COREAON_CLKOUTMUX2_CLKCTRL == 100 
[    3.529642] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
[    3.537821] VFS: Mounted root (ext4 filesystem) on device 179:2.
[    3.551870] devtmpfs: mounted
[    3.555751] Freeing unused kernel memory: 2048K
[    3.560387] Run /sbin/init as init process
[    4.223852] systemd[1]: System time before build time, advancing clock.
[    4.258756] systemd[1]: systemd 239 running in system mode. (+PAM -AUDIT -SELINUX +IMA -APPARMOR +SMACK +SYSVINIT +UTMP -LIBCRYPTSETUP -GCRYPT -GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID -ELFUTILS +KMOD -IDN2 -IDN -PCRE2 default-hierarchy=hybrid)
[    4.280925] systemd[1]: Detected architecture arm.

Welcome to Arago 2019.05!

[    4.313402] systemd[1]: Set hostname to <am57xx-evm>.
[    4.472648] [drm] Cannot find any crtc or sizes
[    4.639548] systemd[1]: File /lib/systemd/system/systemd-journald.service:36 configures an IP firewall (IPAddressDeny=any), but the local system does not support BPF/cgroup based firewalling.
[    4.656763] systemd[1]: Proceeding WITHOUT firewalling in effect! (This warning is only shown for the first loaded unit using IP firewalling.)
[    5.046056] random: systemd: uninitialized urandom read (16 bytes read)
[    5.064057] systemd[1]: Listening on Process Core Dump Socket.
[  OK  ] Listening on Process Core Dump Socket.
[    5.093217] random: systemd: uninitialized urandom read (16 bytes read)
[    5.100048] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[  OK  ] Started Dispatch Password Requests to Console Directory Watch.
[    5.142688] random: systemd: uninitialized urandom read (16 bytes read)
[    5.149363] systemd[1]: Reached target Swap.
[  OK  ] Reached target Swap.
[    5.186186] systemd[1]: Created slice system-getty.slice.
[  OK  ] Created slice system-getty.slice.
[    5.213043] systemd[1]: Listening on Journal Socket (/dev/log).
[  OK  ] Listening on Journal Socket (/dev/log).
[  OK  ] Listening on Network Service Netlink Socket.
[  OK  ] Listening on udev Control Socket.
[  OK  ] Started Forward Password Requests to Wall Directory Watch.
[  OK  ] Listening on udev Kernel Socket.
[  OK  ] Created slice User and Session Slice.
[  OK  ] Reached target Slices.
[  OK  ] Listening on Journal Socket.
[  OK  ] Started Hardware RNG Entropy Gatherer Daemon.
[    5.561321] random: crng init done
[    5.564799] random: 7 urandom warning(s) missed due to ratelimiting
         Starting Create list of required st…ce nodes for the current kernel...
         Mounting Kernel Debug File System...
         Starting Load Kernel Modules...
[    5.709744] cmemk: loading out-of-tree module taints kernel.
[    5.716805] CMEMK module: reference Linux version 4.19.38
[    5.722770] allocated heap buffer 0x40500000 of size 0x100000
[    5.728587] cmemk initialized
         Starting Remount Root and Kernel File Systems...
[    5.746375] EXT4-fs (mmcblk0p2): re-mounted. Opts: (null)
[    5.751964] cryptodev: driver 1.9 loaded.
[  OK  ] Listening on initctl Compatibility Named Pipe.
[  OK  ] Reached target Paths.
[    5.823379] usbcore: registered new interface driver usbfs
[    5.829013] usbcore: registered new interface driver hub
         [    5.834573] usbcore: registered new device driver usb
Mounting POSIX Message Queue File System...
[    5.856921] usbcore: registered new interface driver ftdi_sio
[    5.862787] usbserial: USB Serial support registered for FTDI USB Serial Device
         Mounting Temporary Directory (/tmp)...
         Starting udev Coldplug all Devices...
[  OK  ] Reached target Remote File Systems.
         Starting Journal Service...
[  OK  ] Created slice system-serial\x2dgetty.slice.
[  OK  ] Started Create list of required sta…vice nodes for the current kernel.
[  OK  ] Started Journal Service.
[  OK  ] Mounted Kernel Debug File System.
[  OK  ] Started Load Kernel Modules.
[  OK  ] Started Remount Root and Kernel File Systems.
[  OK  ] Mounted POSIX Message Queue File System.
[  OK  ] Mounted Temporary Directory (/tmp).
         Starting Apply Kernel Variables...
         Mounting Kernel Configuration File System...
         Starting Flush Journal to Persistent Storage...
         Starting Create Static Device Nodes in /dev...
[  OK  ] Started Apply Kernel Variables.
[  OK  ] Mounted Kernel Configuration File System.
[  OK  ] Started Create Static Device Nodes in /dev.
[    6.490282] systemd-journald[101]: Received request to flush runtime journal from PID 1
[  OK  ] Reached target Local File Systems (Pre).
[  OK  ] Reached target Containers.
         Mounting /var/volatile...
         Mounting /media/ram...
         Starting udev Kernel Device Manager...
[  OK  ] Started Flush Journal to Persistent Storage.
[  OK  ] Mounted /var/volatile.
[  OK  ] Mounted /media/ram.
         Starting Load/Save Random Seed...
[  OK  ] Reached target Local File Systems.
         Starting Create Volatile Files and Directories...
[  OK  ] Started udev Kernel Device Manager.
[  OK  ] Started udev Coldplug all Devices.
[  OK  ] Started Load/Save Random Seed.
[  OK  ] Started Create Volatile Files and Directories.
         Starting Update UTMP about System Boot/Shutdown...
         Starting Network Time Synchronization...
         Starting Network Service...
[    7.071509] omap-rproc 58820000.ipu: ignoring dependency for device, assuming no driver
[    7.113211] omap-rproc 58820000.ipu: ignoring dependency for device, assuming no driver
[  OK  ] Started Update UTMP about System Boot/Shutdow[    7.125734] omap-rproc 58820000.ipu: assigned reserved memory node ipu1-memory@9d000000
n.
[    7.151404] remoteproc remoteproc0: 58820000.ipu is available
[    7.204187] omap-rproc 55020000.ipu: ignoring dependency for device, assuming no driver
[  OK  ] Found device /dev/ttyS2.
[    7.260279] omap-rproc 55020000.ipu: ignoring dependency for device, assuming no driver
[    7.317226] omap-rproc 55020000.ipu: assigned reserved memory node ipu2-memory@95800000
[    7.384679] remoteproc remoteproc1: 55020000.ipu is available
[    7.398138] omap-rproc 40800000.dsp: ignoring dependency for device, assuming no driver
[    7.430720] omap-rproc 40800000.dsp: ignoring dependency for device, assuming no driver
[    7.455742] omap-rproc 40800000.dsp: assigned reserved memory node dsp1-memory@99000000
[    7.472818] remoteproc remoteproc2: 40800000.dsp is available
[    7.490427] omap-rproc 41000000.dsp: ignoring dependency for device, assuming no driver
[    7.499482] omap-rproc 41000000.dsp: ignoring dependency for device, assuming no driver
[    7.508271] omap-rproc 41000000.dsp: assigned reserved memory node dsp2-memory@9f000000
[    7.518101] remoteproc remoteproc3: 41000000.dsp is available
[    7.589706] omap_gpio 48057000.gpio: Could not set line 16 debounce to 20000 microseconds (-22)
[    7.601135] palmas-rtc 48070000.i2c:tps659038@58:tps659038_rtc: rtc core: registered 48070000.i2c:tps659038@58:tps659038_rtc as rtc0
[    7.711014] Driver for 1-wire Dallas network protocol.
[    8.004087] omap_rtc 48838000.rtc: registered as rtc1
[    8.032628] omap_hdq 480b2000.1w: OMAP HDQ Hardware Rev 0.:. Driver in Interrupt mode
[    8.243619] w1_master_driver w1_bus_master1: Attaching one wire slave 01.000000000000 crc 3d
[    8.258528] w1_master_driver w1_bus_master1: Family 1 for 01.000000000000.3d is not registered.
[    8.572594] remoteproc remoteproc0: powering up 58820000.ipu
[    8.578292] remoteproc remoteproc0: Booting fw image dra7-ipu1-fw.xem4, size 6704992
[    8.587188] omap-iommu 58882000.mmu: 58882000.mmu: version 2.1
[    8.603132] virtio_rpmsg_bus virtio0: rpmsg host is online
[    8.608676] remoteproc remoteproc0: registered virtio0 (type 7)
[    8.615743] remoteproc remoteproc0: remote processor 58820000.ipu is now up
[  OK  ] Started Network Service.
         Starting Wait for Network to be Configured...
[    8.714128] remoteproc remoteproc1: powering up 55020000.ipu
[    8.721094] remoteproc remoteproc1: Booting fw image dra7-ipu2-fw.xem4, size 3747220
[    8.731259] omap-iommu 55082000.mmu: 55082000.mmu: version 2.1
[    8.738595] virtio_rpmsg_bus virtio0: creating channel rpmsg-proto addr 0x3d
         Starting Network Name Resolution...
[    8.797573] virtio_rpmsg_bus virtio1: rpmsg host is online
[    8.805493] virtio_rpmsg_bus virtio1: creating channel rpmsg-rpc addr 0x65
[    8.805550] remoteproc remoteproc1: registered virtio1 (type 7)
[    8.812513] virtio_rpmsg_bus virtio1: creating channel rpmsg-rpc addr 0x66
[    8.820532] remoteproc remoteproc1: remote processor 55020000.ipu is now up
[    8.879582] omap-des 480a5000.des: OMAP DES hw accel rev: 2.2
[  OK  ] Started Network Time Synchronization.
[    8.888797] omap-des 480a5000.des: will run requests pump with realtime priority
[  OK  ] Reached target System Time Synchronized.
[  OK  ] Reached target System Initialization.
[  OK  ] Started Daily Cleanup of Temporary Directories.
[  OK  ] Started Daily rotation of log files.
[  OK  ] Reached target Timers.
[  OK  ] Listening on RPCbind Server Activation Socket.
[  OK  ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket.
         Starting Reboot and dump vmcore via kexec...
[    9.281737] ov2659 0-0030: Sensor detection failed (3030, 0)
[  OK  ] Listening on D-Bus System Message Bus Socket.
[    9.652637] vpe 489d0000.vpe: loading firmware vpdma-1b8.bin
[    9.662082] omap-sham 4b101000.sham: hw accel on OMAP rev 4.3
[    9.674553] phy phy-4a084000.phy.3: Linked as a consumer to regulator.21
[    9.684107] omap_wdt: OMAP Watchdog Timer Rev 0x01: initial timeout 60 sec
[    9.692675] phy phy-4a085000.phy.4: Linked as a consumer to regulator.21
[    9.708267] CAN device driver interface
[    9.774236] vpe 489d0000.vpe: Device registered as /dev/video0
[    9.890154] SCSI subsystem initialized
[  OK  ] Listening on dropbear.socket.
[  OK  ] Reached target Sockets.
[  OK  ] Reached target Basic System.
[  OK  ] Started D-Bus System Message Bus.
[   10.019590] omap-aes 4b500000.aes: OMAP AES hw accel rev: 3.3
[   10.037028] c_can_platform 4ae3c000.can: c_can_platform device registered (regs=636694fe, irq=89)
[   10.042626] omap-aes 4b500000.aes: will run requests pump with realtime priority
         Starting TI MultiCore Tools Daemon...
[   10.069509] omap-aes 4b700000.aes: OMAP AES hw accel rev: 3.3
[   10.075585] omap-aes 4b700000.aes: will run requests pump with realtime priority
         Starting rng-tools.service...
         Starting RPC Bind Service...
[   10.307800] vip 48990000.vip: loading firmware vpdma-1b8.bin
         Starting TI IPC Daemon...
[   10.342625] vip 48990000.vip: VPDMA firmware loaded
[  OK  ] Started Periodic Command Scheduler.
[  OK  ] Started Job spooling tools.
         Starting uim-sysfs.service...
         Starting Login Service...
         Starting Print notice about GPLv3 packages...
[  OK  ] Started Network Name Resolution.
[  OK  ] Reached target Host and Network Name Lookups.
         Starting Avahi mDNS/DNS-SD Stack...
[  OK  ] Reached target Network.
         Starting Simple Network Management Protocol (SNMP) Daemon....
         Starting Enable and configure wl18xx bluetooth stack...
         Starting Lightning Fast Webserver With Light System Requirements...
         Starting Permit User Sessions...
[  OK  ] Started Redis In-Memory Data Store.
[   11.054230] net eth0: initializing cpsw version 1.15 (0)
[   11.193166] Micrel KSZ9031 Gigabit PHY 48485000.mdio:00: attached PHY driver [Micrel KSZ9031 Gigabit PHY] (mii_bus:phy_addr=48485000.mdio:00, irq=POLL)
[   11.231508] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[   11.273473] remoteproc remoteproc2: powering up 40800000.dsp
[   11.280252] remoteproc remoteproc2: Booting fw image dra7-dsp1-fw.xe66, size 20384656
[   11.303333] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
[   11.309220] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0
[   11.332629] net eth1: initializing cpsw version 1.15 (0)
[   11.351453] virtio_rpmsg_bus virtio2: rpmsg host is online
[   11.353947] virtio_rpmsg_bus virtio2: creating channel rpmsg-proto addr 0x3d
[   11.357470] remoteproc remoteproc2: registered virtio2 (type 7)
[   11.413266] remoteproc remoteproc2: remote processor 40800000.dsp is now up
[   11.438586] ahci 4a140000.sata: forcing port_map 0x0 -> 0x1
[   11.446247] ahci 4a140000.sata: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl platform mode
[   11.470017] ahci 4a140000.sata: flags: 64bit ncq sntf pm led clo only pmp pio slum part ccc apst 
[   11.485012] Micrel KSZ9031 Gigabit PHY 48485000.mdio:01: attached PHY driver [Micrel KSZ9031 Gigabit PHY] (mii_bus:phy_addr=48485000.mdio:01, irq=POLL)
[   11.504567] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
[   11.517636] scsi host0: ahci
[   11.520838] ata1: SATA max UDMA/133 mmio [mem 0x4a140000-0x4a1410ff] port 0x100 irq 81
[   11.569222] remoteproc remoteproc3: powering up 41000000.dsp
[   11.584503] remoteproc remoteproc3: Booting fw image dra7-dsp2-fw.xe66, size 20384656
[   11.611615] omap-iommu 41501000.mmu: 41501000.mmu: version 3.0
[   11.617578] omap-iommu 41502000.mmu: 41502000.mmu: version 3.0
[   11.678620] omap-hdmi-audio omap-hdmi-audio.0.auto: snd-soc-dummy-dai <-> 58040000.encoder mapping ok
[   11.706452] [drm] Initialized pvr 1.17.4948957 20110701 for 56000000.gpu on minor 1
[   11.731403] omap-hdmi-audio omap-hdmi-audio.0.auto: ASoC: no DMI vendor name!
[   11.781622] virtio_rpmsg_bus virtio3: rpmsg host is online
[   11.781701] virtio_rpmsg_bus virtio3: creating channel rpmsg-proto addr 0x3d
[   11.787295] remoteproc remoteproc3: registered virtio3 (type 7)
[   11.800563] remoteproc remoteproc3: remote processor 41000000.dsp is now up
[   11.892644] ata1: SATA link down (SStatus 0 SControl 300)
[   12.142604] davinci_mdio 4b2b2400.mdio: davinci mdio revision 1.6, bus freq 1000000
[   12.153471] libphy: 4b2b2400.mdio: probed
[   12.166733] davinci_mdio 4b2b2400.mdio: phy[0]: device 4b2b2400.mdio:00, driver TI TLK10X 10/100 Mbps PHY
[   12.180378] davinci_mdio 4b2b2400.mdio: phy[1]: device 4b2b2400.mdio:01, driver TI TLK10X 10/100 Mbps PHY
[   12.237079] remoteproc remoteproc4: 4b234000.pru is available
[   12.278570] pru-rproc 4b234000.pru: PRU rproc node pru@4b234000 probed successfully
[   12.310259] remoteproc remoteproc5: 4b238000.pru is available
[   12.366615] pru-rproc 4b238000.pru: PRU rproc node pru@4b238000 probed successfully
[   12.441369] remoteproc remoteproc6: 4b2b4000.pru is available
[  OK  ] Started Login Service.
[  OK  ] Started Reboot and dump vmcore via kexec.
[  OK  ] Started TI MultiCore Tools Daemon.
[  OK  ] Started rng-tools.service.
[  OK  ] Started RPC Bind Service.
[  OK  ] Started TI IPC Daemon.
[   12.510519] pru-rproc 4b2b4000.pru: PRU rproc node pru@4b2b4000 probed successfully
[  OK  ] Started uim-sysfs.service.
[  OK  ] Started Enable and configure wl18xx bluetooth stack.
[   12.576106] remoteproc remoteproc7: 4b2b8000.pru is available
[  OK  ] Started Lightning Fast Webserver With Light System Requirements.
[  OK  ] Started Permit User Sessions.
[   12.642925] pru-rproc 4b2b8000.pru: PRU rproc node pru@4b2b8000 probed successfully
[   12.976877] prueth pruss2_eth: pruss_fw_drop_untagged_vlan 0
[   12.993059] prueth pruss2_eth: pruss MC Mask (Port 0) ff:ff:ff:ff:ff:ff
[   13.024686] prueth pruss2_eth: pruss MC Mask (Port 1) ff:ff:ff:ff:ff:ff
[   13.031348] prueth pruss2_eth: request for sync latch pins failed: -19
[   13.092160] prueth pruss2_eth: TI PRU ethernet (type 0) driver initialized
[   13.653128] rpmsg_rpc virtio1.rpmsg-rpc.-1.101: probing service dce-callback with src 1024 dst 101
[   13.674405] dwc3 48890000.usb: Failed to get clk 'ref': -2
[   13.674560] NET: Registered protocol family 45
[   13.685919] rpmsg_rpc virtio1.rpmsg-rpc.-1.102: probing service rpmsg-dce with src 1025 dst 102
[   13.696593] rpmsg_rpc virtio1.rpmsg-rpc.-1.101: published functions = 4
[   13.723753] dwc3 488d0000.usb: Failed to get clk 'ref': -2
[   13.752020] rpmsg_rpc virtio1.rpmsg-rpc.-1.102: published functions = 9
[   13.968324] pruss_intc_irq_set_affinity: event 21 not configured: ch = -1, host = -1
[   13.978265] pruss_intc_irq_set_affinity: event 23 not configured: ch = -1, host = -1
[   13.988953] pruss_intc_irq_set_affinity: event 27 not configured: ch = -1, host = -1
[   14.001987] iep ptp bc clkid -1
[   14.005356] remoteproc remoteproc7: powering up 4b2b8000.pru
[   14.029193] remoteproc remoteproc7: Booting fw image ti-pruss/am57xx-pru1-prueth-fw.elf, size 6344
[   14.039596] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[   14.047341] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 1
[   14.056885] pruss 4b280000.pruss: configured system_events[63-0] = 0x00600000.08a00000
[   14.065664] pruss 4b280000.pruss: configured intr_channels = 0x0000032a host_intr = 0x000002aa
[   14.075256] remoteproc remoteproc7: remote processor 4b2b8000.pru is now up
[   14.083134] net eth3: started
[   14.087082] xhci-hcd xhci-hcd.1.auto: hcc params 0x0220f04c hci version 0x100 quirks 0x0000000002010010
[   14.097301] IPv6: ADDRCONF(NETDEV_UP): eth3: link is not ready
[   14.104452] xhci-hcd xhci-hcd.1.auto: irq 181, io mem 0x48890000
[   14.117641] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 4.19
[   14.126034] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[  OK  ] Started Simple Network Management Protocol (S[   14.134060] usb usb1: Product: xHCI Host Controller
NMP) Daemon..
[   14.143995] usb usb1: Manufacturer: Linux 4.19.38-g4dae378bbe xhci-hcd
[   14.151830] usb usb1: SerialNumber: xhci-hcd.1.auto
[   14.159219] pruss_intc_irq_set_affinity: event 20 not configured: ch = -1, host = -1
[   14.161341] hub 1-0:1.0: USB hub found
[   14.168833] pruss_intc_irq_set_affinity: event 22 not configured: ch = -1, host = -1
[   14.171458] hub 1-0:1.0: 1 port detected
[   14.179483] pruss_intc_irq_set_affinity: event 26 not configured: ch = -1, host = -1
[   14.190858] remoteproc remoteproc6: powering up 4b2b4000.pru
[   14.191397] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[   14.202094] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 2
[   14.210084] xhci-hcd xhci-hcd.1.auto: Host supports USB 3.0  SuperSpeed
[   14.216828] remoteproc remoteproc6: Booting fw image ti-pruss/am57xx-pru0-prueth-fw.elf, size 6316
[   14.216985] pruss 4b280000.pruss: configured system_events[63-0] = 0x00000600.04500000
[   14.226464] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[   14.242157] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 4.19
[   14.250525] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[   14.251189] pruss 4b280000.pruss: configured intr_channels = 0x000000d5 host_intr = 0x00000155
[   14.257810] usb usb2: Product: xHCI Host Controller
[   14.271525] usb usb2: Manufacturer: Linux 4.19.38-g4dae378bbe xhci-hcd
[   14.278118] usb usb2: SerialNumber: xhci-hcd.1.auto
[   14.283285] remoteproc remoteproc6: remote processor 4b2b4000.pru is now up
[   14.283539] hub 2-0:1.0: USB hub found
[   14.294212] hub 2-0:1.0: 1 port detected
[   14.300524] net eth2: started
[   14.315798] IPv6: ADDRCONF(NETDEV_UP): eth2: link is not ready
[  OK  ] Started Avahi mDNS/DNS-SD Stack.
         Starting Save/Restore Sound Card State...
[  OK  ] Created slice system-systemd\x2dfsck.slice.
         Starting File System Check on /dev/mmcblk0p1...
[  OK  ] Listening on Load/Save RF Kill Switch Status /dev/rfkill Watch.
[  OK  ] Started Serial Getty on ttyS2.
[  OK  ] Started Getty on tty1.
[  OK  ] Reached target Login Prompts.
         Starting Synchronize System and HW clocks...
[  OK  ] Started NFS status monitor for NFSv2/3 locking..
         Starting rc.pvr.service...
[  OK  ] Started Save/Restore Sound Card State.
[  OK  ] Started Synchronize System and HW clocks.
[  OK  ] Reached target Sound Card.
[   17.201465] PVR_K: UM DDK-(4948957) and KM DDK-(4948957) match. [ OK ]
[  OK  ] Started rc.pvr.service.
         Starting weston.service...
[  OK  ] Started File System Check on /dev/mmcblk0p1.
         Mounting /run/media/mmcblk0p1...
[  OK  ] Mounted /run/media/mmcblk0p1.
***************************************************************
***************************************************************
NOTICE: This file system contains the following GPLv3 packages:
	autoconf
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	bash
	bc
	binutils-dev
	binutils
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	swig
	which

If you do not wish to distribute GPLv3 components please remove
the above packages prior to distribution.  This can be done using
the opkg remove command.  i.e.:
    opkg remove <package>
Where <package> is the name printed in the list above

NOTE: If the package is a dependency of another package you
      will be notified of the dependent packages.  You should
      use the --force-removal-of-dependent-packages option to
      also remove the dependent packages as well
***************************************************************
***************************************************************
[  OK  ] Started Print notice about GPLv3 packages.
[  OK  ] Started weston.service.
         Starting Matrix GUI...
         Starting telnetd.service...
[  OK  ] Started Matrix GUI.
[  OK  ] Started telnetd.service.
         Starting thttpd.service...
[  OK  ] Started thttpd.service.

 _____                    _____           _         _   
|  _  |___ ___ ___ ___   |  _  |___ ___  |_|___ ___| |_ 
|     |  _| .'| . | . |  |   __|  _| . | | | -_|  _|  _|
|__|__|_| |__,|_  |___|  |__|  |_| |___|_| |___|___|_|  
              |___|                    |___|            

Arago Project http://arago-project.org am57xx-evm ttyS2

Arago 2019.05 am57xx-evm ttyS2

am57xx-evm login: root
root@am57xx-evm:~# devmem2 0x4AE061C8
/dev/mem opened.
Memory mapped at address 0xb6fd7000.
Read at address  0x4AE061C8 (0xb6fd71c8): 0x00000001
root@am57xx-evm:~# devmem2 0x4A0086B0
/dev/mem opened.
Memory mapped at address 0xb6fca000.
Read at address  0x4A0086B0 (0xb6fca6b0): 0x00000100
root@am57xx-evm:~#

- clk-7xx.c file

Fullscreen clk-7xx.c Download

/*
 * DRA7 Clock init
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 *
 * Tero Kristo (t-kristo@ti.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk/ti.h>
#include <dt-bindings/clock/dra7.h>

#include "clock.h"

#define DRA7_DPLL_GMAC_DEFFREQ				1000000000
#define DRA7_DPLL_USB_DEFFREQ				960000000

static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
	{ DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = {
	{ DRA7_DSP1_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = {
	{ DRA7_DSP2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },
	{ 0 },
};

static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = {
	"dpll_abe_m2x2_ck",
	"dpll_core_h22x2_ck",
	NULL,
};

static const struct omap_clkctrl_bit_data dra7_ipu1_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = {
	{ DRA7_IPU1_CLKCTRL, dra7_ipu1_bit_data, CLKF_HW_SUP | CLKF_NO_IDLEST, "ipu1_cm:clk:0000:24", "ipu1_clkdm" },
	{ 0 },
};

static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
	"per_abe_x1_gfclk2_div",
	"video1_clk2_div",
	"video2_clk2_div",
	"hdmi_clk2_div",
	NULL,
};

static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
	"abe_24m_fclk",
	"abe_sys_clk_div",
	"func_24m_clk",
	"atl_clkin3_ck",
	"atl_clkin2_ck",
	"atl_clkin1_ck",
	"atl_clkin0_ck",
	"sys_clkin2",
	"ref_clkin0_ck",
	"ref_clkin1_ck",
	"ref_clkin2_ck",
	"ref_clkin3_ck",
	"mlb_clk",
	"mlbp_clk",
	NULL,
};

static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
	{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
	{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
	{ 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
	{ 0 },
};

static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
	"timer_sys_clk_div",
	"sys_32k_ck",
	"sys_clkin2",
	"ref_clkin0_ck",
	"ref_clkin1_ck",
	"ref_clkin2_ck",
	"ref_clkin3_ck",
	"abe_giclk_div",
	"video1_div_clk",
	"video2_div_clk",
	"hdmi_div_clk",
	"clkoutmux0_clk_mux",
	NULL,
};

static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
	{ 0 },
};

static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
	"func_48m_fclk",
	"dpll_per_m2x2_ck",
	NULL,
};

static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
	{ DRA7_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0010:22" },
	{ DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" },
	{ DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" },
	{ DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" },
	{ DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" },
	{ DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
	{ DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
	{ DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
	{ DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
	{ DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
	{ DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
	{ DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
	{ DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
	{ DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = {
	{ DRA7_IPU2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
	{ DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
	{ DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ 0 },
};

static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
	"sys_32k_ck",
	"video1_clkin_ck",
	"video2_clkin_ck",
	"hdmi_clkin_ck",
	NULL,
};

static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
	"l3_iclk_div",
	"dpll_abe_m2_ck",
	"atl_cm:clk:0000:24",
	NULL,
};

static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
	{ 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
	{ DRA7_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl_cm:clk:0000:26" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
	{ DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
	{ DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
	{ DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
	{ 0 },
};

static const char * const dra7_dss_dss_clk_parents[] __initconst = {
	"dpll_per_h12x2_ck",
	NULL,
};

static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
	"func_48m_fclk",
	NULL,
};

static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
	"hdmi_dpll_clk_mux",
	NULL,
};

static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
	"sys_32k_ck",
	NULL,
};

static const char * const dra7_dss_video1_clk_parents[] __initconst = {
	"video1_dpll_clk_mux",
	NULL,
};

static const char * const dra7_dss_video2_clk_parents[] __initconst = {
	"video2_dpll_clk_mux",
	NULL,
};

static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
	{ 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
	{ 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
	{ 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
	{ 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
	{ 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
	{ DRA7_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
	{ DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
	{ 0 },
};

static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
	"func_128m_clk",
	"dpll_per_m2x2_ck",
	NULL,
};

static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
	"l3init_cm:clk:0008:24",
	NULL,
};

static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {
	.max_div = 4,
	.flags = CLK_DIVIDER_POWER_OF_TWO,
};

static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
	{ 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
	{ 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data },
	{ 0 },
};

static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
	"l3init_cm:clk:0010:24",
	NULL,
};

static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {
	.max_div = 4,
	.flags = CLK_DIVIDER_POWER_OF_TWO,
};

static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
	{ 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
	{ 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data },
	{ 0 },
};

static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
	"l3init_960m_gfclk",
	NULL,
};

static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
	{ 0 },
};

static const char * const dra7_sata_ref_clk_parents[] __initconst = {
	"sys_clkin1",
	NULL,
};

static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
	{ 0 },
};

static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
	"apll_pcie_ck",
	NULL,
};

static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
	"optfclk_pciephy_div",
	NULL,
};

static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
	{ 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
	{ 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
	{ 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
	{ 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
	{ 0 },
};

static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
	"dpll_gmac_h11x2_ck",
	"rmii_clk_ck",
	NULL,
};

static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
	"video1_clkin_ck",
	"video2_clkin_ck",
	"dpll_abe_m2_ck",
	"hdmi_clkin_ck",
	"l3_iclk_div",
	NULL,
};

static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
	{ 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
	{ DRA7_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
	{ DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
	{ DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
	{ DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
	{ DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" },
	{ DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
	{ DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
	{ DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
	{ DRA7_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck", "gmac_clkdm" },
	{ DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
	{ DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
	{ DRA7_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
	{ 0 },
};

static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
	"timer_sys_clk_div",
	"sys_32k_ck",
	"sys_clkin2",
	"ref_clkin0_ck",
	"ref_clkin1_ck",
	"ref_clkin2_ck",
	"ref_clkin3_ck",
	"abe_giclk_div",
	"video1_div_clk",
	"video2_div_clk",
	"hdmi_div_clk",
	NULL,
};

static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
	{ 0 },
};

static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
	"l4per_cm:clk:0120:24",
	NULL,
};

static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {
	.max_div = 4,
	.flags = CLK_DIVIDER_POWER_OF_TWO,
};

static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
	{ 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data },
	{ 0 },
};

static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
	"l4per_cm:clk:0128:24",
	NULL,
};

static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {
	.max_div = 4,
	.flags = CLK_DIVIDER_POWER_OF_TWO,
};

static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
	{ 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
	{ 0 },
};

static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
	"func_128m_clk",
	"dpll_per_h13x2_ck",
	NULL,
};

static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
	"l4per_cm:clk:0138:24",
	NULL,
};

static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
	.max_div = 4,
	.flags = CLK_DIVIDER_POWER_OF_TWO,
};

static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
	{ 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
	{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
	{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
	{ 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
	{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
	{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
	{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
	{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
	{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
	{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
	{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
	{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
	{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
	{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
	{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
	{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
	{ DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" },
	{ DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" },
	{ DRA7_PRUSS1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_gmac_h13x2_ck" },
	{ DRA7_PRUSS2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_gmac_h13x2_ck" },
	{ DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
	{ DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
	{ DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" },
	{ DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" },
	{ DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" },
	{ DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" },
	{ DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
	{ DRA7_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
	{ DRA7_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
	{ DRA7_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
	{ DRA7_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
	{ DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
	{ DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
	{ DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
	{ DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
	{ DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
	{ DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
	{ DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
	{ DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
	{ DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm" },
	{ DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm" },
	{ DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm" },
	{ DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
	{ DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
	{ DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
	{ DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
	{ DRA7_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
	{ DRA7_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
	{ DRA7_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0120:25" },
	{ DRA7_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0128:25" },
	{ DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm" },
	{ DRA7_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0138:25", "l4per2_clkdm" },
	{ DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" },
	{ DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" },
	{ DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" },
	{ DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" },
	{ DRA7_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0160:22", "l4per2_clkdm" },
	{ DRA7_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0168:22", "l4per2_clkdm" },
	{ DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" },
	{ DRA7_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0178:22", "l4per2_clkdm" },
	{ DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" },
	{ DRA7_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0198:22", "l4per2_clkdm" },
	{ DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
	{ DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
	{ DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
	{ DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div", "l4sec_clkdm" },
	{ DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
	{ DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },
	{ DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
	{ DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" },
	{ DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" },
	{ DRA7_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0204:22", "l4per2_clkdm" },
	{ DRA7_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0208:22", "l4per2_clkdm" },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
	{ 0 },
};

static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
	"sys_clkin1",
	"sys_clkin2",
	NULL,
};

static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
	{ DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
	{ DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
	{ DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
	{ DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
	{ DRA7_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },
	{ DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
	{ DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },
	{ DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },
	{ DRA7_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk"},
	{ 0 },
};

const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
	{ 0x4a005320, dra7_mpu_clkctrl_regs },
	{ 0x4a005420, dra7_dsp1_clkctrl_regs },
	{ 0x4a005520, dra7_ipu1_clkctrl_regs },
	{ 0x4a005540, dra7_ipu_clkctrl_regs },
	{ 0x4a005620, dra7_dsp2_clkctrl_regs },
	{ 0x4a005740, dra7_rtc_clkctrl_regs },
	{ 0x4a008620, dra7_coreaon_clkctrl_regs },
	{ 0x4a008720, dra7_l3main1_clkctrl_regs },
	{ 0x4a008920, dra7_ipu2_clkctrl_regs },
	{ 0x4a008a20, dra7_dma_clkctrl_regs },
	{ 0x4a008b20, dra7_emif_clkctrl_regs },
	{ 0x4a008c00, dra7_atl_clkctrl_regs },
	{ 0x4a008d20, dra7_l4cfg_clkctrl_regs },
	{ 0x4a008e20, dra7_l3instr_clkctrl_regs },
	{ 0x4a009120, dra7_dss_clkctrl_regs },
	{ 0x4a009320, dra7_l3init_clkctrl_regs },
	{ 0x4a009700, dra7_l4per_clkctrl_regs },
	{ 0x4ae07820, dra7_wkupaon_clkctrl_regs },
	{ 0 },
};

static struct ti_dt_clk dra7xx_clks[] = {
	DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
	DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
	DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
	DT_CLK("4ae18000.timer", "timer_sys_ck", "timer_sys_clk_div"),
	DT_CLK("48032000.timer", "timer_sys_ck", "timer_sys_clk_div"),
	DT_CLK("48034000.timer", "timer_sys_ck", "timer_sys_clk_div"),
	DT_CLK("48036000.timer", "timer_sys_ck", "timer_sys_clk_div"),
	DT_CLK("4803e000.timer", "timer_sys_ck", "timer_sys_clk_div"),
	DT_CLK("48086000.timer", "timer_sys_ck", "timer_sys_clk_div"),
	DT_CLK("48088000.timer", "timer_sys_ck", "timer_sys_clk_div"),
	DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"),
	DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"),
	DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"),
	DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"),
	DT_CLK("48828000.timer", "timer_sys_ck", "timer_sys_clk_div"),
	DT_CLK("4882a000.timer", "timer_sys_ck", "timer_sys_clk_div"),
	DT_CLK("4882c000.timer", "timer_sys_ck", "timer_sys_clk_div"),
	DT_CLK("4882e000.timer", "timer_sys_ck", "timer_sys_clk_div"),
	DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"),
	DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"),
	DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"),
	DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
	DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
	DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
	DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"),
	DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"),
	DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"),
	DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"),
	DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
	DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"),
	DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"),
	DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"),
	DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"),
	DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"),
	DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"),
	DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"),
	DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1_cm:0000:24"),
	DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"),
	DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"),
	DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"),
	DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"),
	DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"),
	DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"),
	DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"),
	DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"),
	DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"),
	DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"),
	DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"),
	DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"),
	DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"),
	DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"),
	DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"),
	DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"),
	DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"),
	DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"),
	DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"),
	DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"),
	DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
	DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"),
	DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"),
	DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
	DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"),
	DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"),
	DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"),
	DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"),
	DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"),
	DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"),
	DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"),
	DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"),
	DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"),
	DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"),
	DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"),
	DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"),
	DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"),
	DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"),
	DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"),
	DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
	DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"),
	DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"),
	DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"),
	DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"),
	DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"),
	DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"),
	DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
	DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"),
	DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"),
	DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"),
	DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"),
	DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"),
	DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"),
	DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"),
	DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"),
	DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"),
	DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"),
	DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"),
	DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"),
	DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"),
	DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"),
	DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"),
	DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"),
	DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"),
	DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"),
	DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"),
	DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"),
	{ .node_name = NULL },
};

int __init dra7xx_dt_clk_init(void)
{
	int rc;
	struct clk *dpll_ck, *hdcp_ck;
         
        static void __iomem *reg1_base;
        static void __iomem *reg2_base;

        uint32_t value;

	ti_dt_clocks_register(dra7xx_clks);

	omap2_clk_disable_autoidle_all();

	ti_clk_add_aliases();

	dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
	rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
	if (rc)
		pr_err("%s: failed to configure GMAC DPLL!\n", __func__);

	dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
	rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
	if (rc)
		pr_err("%s: failed to configure USB DPLL!\n", __func__);

	dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
	rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
	if (rc)
		pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);

	hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
	rc = clk_prepare_enable(hdcp_ck);
	if (rc)
		pr_err("%s: failed to set dss_deshdcp_clk\n", __func__);
         
        printk("dra7xx_dt_clk_init() -> register write\n");
        
        reg1_base = ioremap(0x4A0086B0,4);  //CM_COREAON_CLKOUTMUX2_CLKCTRL
        value =  __raw_readl(reg1_base); 
        printk("default CM_COREAON_CLKOUTMUX2_CLKCTRL == %x \n",value);
        __raw_writel(0x100,reg1_base);
        value =  __raw_readl(reg1_base); 
        printk("updated CM_COREAON_CLKOUTMUX2_CLKCTRL == %x \n",value);
        
        reg2_base = ioremap(0x4AE061C8,4);  //CM_CLKSEL_SYS_CLK1_CLKOUTMUX
        value =  __raw_readl(reg2_base);
        printk("default CM_CLKSEL_SYS_CLK1_CLKOUTMUX == %x \n",value);
	__raw_writel(0x1,reg2_base);
        value =  __raw_readl(reg2_base);
        printk("updated CM_CLKSEL_SYS_CLK1_CLKOUTMUX == %x \n",value);

        return rc;
}

- last.c

Fullscreen last.c Download

/*
 *  Advanced Linux Sound Architecture
 *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
 *
 *
 *   This program is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation; either version 2 of the License, or
 *   (at your option) any later version.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 *
 *   You should have received a copy of the GNU General Public License
 *   along with this program; if not, write to the Free Software
 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 */

#include <linux/init.h>
#include <sound/core.h>

#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk/ti.h>
#include <dt-bindings/clock/dra7.h>



static int __init alsa_sound_last_init(void)
{
	int idx, ok = 0;
        
        static void __iomem *reg1_base;
        uint32_t value;
	
	printk(KERN_INFO "ALSA device list:\n");
	for (idx = 0; idx < SNDRV_CARDS; idx++)
		if (snd_cards[idx] != NULL) {
			printk(KERN_INFO "  #%i: %s\n", idx, snd_cards[idx]->longname);
			ok++;
		}
	if (ok == 0)
		printk(KERN_INFO "  No soundcards found.\n");

        printk("alsa_sound_last_init() -> register write\n");
        
        reg1_base = ioremap(0x4A0086B0,4);  //CM_COREAON_CLKOUTMUX2_CLKCTRL
        value =  __raw_readl(reg1_base); 
        printk("default CM_COREAON_CLKOUTMUX2_CLKCTRL == %x \n",value);
        __raw_writel(0x100,reg1_base);
        value =  __raw_readl(reg1_base); 
        printk("updated CM_COREAON_CLKOUTMUX2_CLKCTRL == %x \n",value);

	return 0;
}

late_initcall_sync(alsa_sound_last_init);

Regards,
Pavel

0 satheesh kumar32 over 5 years ago in reply to Pavel Botev

Expert 1045 points

Hi Pavel

This modification works well.

I appreciate your continuous support.

Regards

Satheesh Kumar S

0 satheesh kumar32 over 5 years ago in reply to satheesh kumar32

Expert 1045 points

Hi Pavel

I have to interface TLV320AIC3106 audio codec with AM5718 IDK for exploring audio functionality before our custom board arrived. For that, I have selected clockout2(10MHz),I2c1 and McASP3 as interface. I have configured kernel (menu config )as mentioned in SDK documentation. Will this configuration works?. Can you suggest suitable audio node configuration in DTS file(AM571x).

Regards

Satheesh Kumar S

0 satheesh kumar32 over 5 years ago in reply to satheesh kumar32

Expert 1045 points

Hi Pavel

Regards

Satheesh Kumar S

0 Pavel Botev over 5 years ago in reply to satheesh kumar32

TI__Guru**** 170625 points

Satheesh Kumar,

I would suggest you to create new e2e post for your new question.

Regards,
Pavel

0 satheesh kumar32 over 5 years ago in reply to Pavel Botev

Expert 1045 points

Hi pavel

I need your help .

I have some question regarding the audio codec (TLV320AIC3106) interfacing mentioned in above case.

My configuration is

system clock 1=20MHz

system clock2 = 24.576MHz(externally feeds with generator)

clockout2----->codec MCLK(12.288MHz)

McASP3 as Master and codec as slave(Both bit clock and frame sync)

Frame sync =48KHz

bitclock = 48KHz*2*32=3.072MHz

As from our previous discussion,whenever all nodes come, the register(CM_COREAON_CLKOUTMUX2_CLKCTRL) will update through DTS. Now I have created a custom design similar to AM5728-GP-EVM as mentioned above. No clock at CLOCKOUT2 through DTS. Register writing Still possible in last.c.

sound0: sound0 {

compatible = "simple-audio-card";
simple-audio-card,name = "BeagleBoard-X15";
simple-audio-card,widgets =
"Line", "Line Out",
"Line", "Line In";
simple-audio-card,routing =
"Line Out", "LLOUT",
"Line Out", "RLOUT",
"MIC2L", "Line In",
"MIC2R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound0_master>;
simple-audio-card,frame-master = <&sound0_master>;
simple-audio-card,bitclock-inversion;

simple-audio-card,cpu {
sound-dai = <&mcasp3>;
};

sound0_master: simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
clocks = <&clkout2_clk>;
};
};

tlv320aic3106: tlv320aic3106@18 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x18>;

assigned-clocks = <&clkoutmux2_clk_mux>;
assigned-clock-parents = <&sys_clk2_dclk_div>;
status = "okay";
adc-settle-ms = <40>;

AVDD-supply = <&vdd_3v3>; //vdd_3v3 v3_3d
IOVDD-supply = <&vdd_3v3>;
DRVDD-supply = <&vdd_3v3>;
DVDD-supply = <&aic_dvdd>; //aic_dvdd ldo2_reg
};

With this device node i can update

CM_CLKSEL_CLKOUTMUX2 (0x4AE06160) to 0x1

But I cannot update CM_COREAON_CLKOUTMUX2_CLKCTRL

I have gone through the following document

http://processors.wiki.ti.com/index.php/Sitara_Linux_Audio_DAC_Example

Interfacing DRA7xx Audio to Analog Codecs

I have some question

1) For integrating TLV320AIC3106 with AM5718 ,is there any kernel source modification is needed(davinci-evm.c,davinci-mcasp.c) as mentioned in the document.

2) SDK contain one defconfig file for all these board,porting instruction given in the SDK linux documentation will work without any kernel source modification.If any correction in my thought,pl z clarify.

2)with device tree,How can I configure McSAP as Master and codec as slave, and bit clock as 3.072MHz,Frame sync =48KHz.

Since you know my previous case,I expect your response.Please help

Regards

Satheesh Kumar S

0 Pavel Botev over 5 years ago in reply to satheesh kumar32

TI__Guru**** 170625 points

Satheesh Kumar,

I would suggest you to create new e2e post for your new question.

Regards,
Pavel

0 satheesh kumar32 over 5 years ago in reply to Pavel Botev

Expert 1045 points

Hi Pavel

I put it in ask similar questions

Plz respond

Regards

Satheesh kumar

0 Pavel Botev over 5 years ago in reply to satheesh kumar32

TI__Guru**** 170625 points

Satheesh Kumar,

I see your new e2e thread (link below). I will reply on this e2e thread and will close this one.

https://e2e.ti.com/support/processors/f/791/t/853382

Regards,
Pavel

0 satheesh kumar32 over 5 years ago in reply to Pavel Botev

Expert 1045 points

Hi Pavel

Ok Thanks

Regards

Satheesh Kumar S

Processors

Processors forum

AM5718: CLKOUT2 issue