TMS320C6678: DDR3 Leveling

ddr3_pll_init(11, 0);

static void ddr3_pll_init(unsigned int multiplier, unsigned int divider)
{
    LOG("DDR3 PLL (PLL2) Setup, mul: %d, div: %d, output Clock: %d Mhz\r\n", multiplier, divider, (int)(66.667*(multiplier+1)/(divider+1)/2.0));
    /*Unlock Boot Config*/
    KICK0 = KICK0_UNLOCK;
    KICK1 = KICK1_UNLOCK;

    /* Usage Note 9: For optimal PLL operation, the ENSAT bit in the PLL control *
     * registers for the Main PLL, DDR3 PLL, and PA PLL should be set to 1.      *
     * The PLL initialization sequence in the boot ROM sets this bit to 0 and    *
     * could lead to non-optimal PLL operation. Software can set the bit to the  *
     * optimal value of 1 after boot                                             *
     * DDR3PLLCTL1 Bit map                                                         *
     * |31...7   |6     |5 4       |3...0      |                                 *
     * |Reserved |ENSAT |Reserved  |BWADJ[11:8]|                                 */
    DDR3PLLCTL1 |= 0x00000040;

    /* Put the PLL in BYPASS Mode                                                   *
     * DDR3PLLCTL0 Bit map                                                         *
     * |31...24    |23     |22...19       |18...6   |5...0 |                     *
     * |BWADJ[7:0] |BYPASS |Reserved      |PLLM     |PLLD  |                     */
    DDR3PLLCTL0 |= 0x00800000; /* Set the Bit 23 */

    /* Program the necessary multipliers/dividers and BW adjustments             */
    /* Set the divider values */
    DDR3PLLCTL0 &= ~(0x0000003F);
    DDR3PLLCTL0 |= (divider & 0x0000003F);

    /* Set the Multipler values */
    DDR3PLLCTL0 &= ~(0x0007FFC0);
    DDR3PLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );

    /* Set the BWADJ */
    uint32_t temp = ((multiplier + 1) >> 1) - 1;
    DDR3PLLCTL0 &= ~(0xFF000000);
    DDR3PLLCTL0 |= ((temp << 24) & 0xFF000000);
    DDR3PLLCTL1 &= ~(0x0000000F);
    DDR3PLLCTL1 |= ((temp >> 8) & 0x0000000F);

    /* In PLL Controller, reset the PLL (bit 13 in DDR3PLLCTL1 register)         */
    DDR3PLLCTL1 |= 0x00002000;

    /* Wait for the PLL Reset time (min: 5 us)                                */
    Delay_milli_seconds(1);

    /*In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset */
    DDR3PLLCTL1 &= ~(0x00002000);

    /* Wait at least 500 * REFCLK cycles * PLLD (this is the PLL lock time) */
    Delay_milli_seconds(1);

    /* Put the PLL in PLL Mode                                                   *
     * DDR3PLLCTL0 Bit map                                                         *
     * |31...24    |23     |22...19       |18...6   |5...0 |                     *
     * |BWADJ[7:0] |BYPASS |Reserved      |PLLM     |PLLD  |                     */
    DDR3PLLCTL0 &= ~(0x00800000); /* ReSet the Bit 23 */
    LOG("DDR3 PLL Setup... Done.\r\n");

    xmc_setup();
}