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Original question:

PROCESSOR-SDK-DRA8X-TDA4X: ECC implementation on LPDDR4

PROCESSOR-SDK-DRA8X-TDA4X: ECC implementation on TI TDA4x series

Vaibhav Kange
Prodigy 100 points

Part Number: PROCESSOR-SDK-DRA8X-TDA4X

DO TI have ECC documentation for TDA4x series ? How can i have it?

  • 0
    TI__Mastermind 23125 points

    Vaibhav, 

    As mentioned in the earlier thread, there is no separate ECC documentation other than Chapter 12.11.4 (ECC Aggregator for MSMC) and Chapter 8.1 (MSMC); Chapter 8.2 (DDR). 

    Next level would be software examples as I mentioned in the PDK in the earlier thread. 

    jian

  • 0 in reply to jian35385
    Prodigy 100 points

    JIan,

    Yes, i have gone through chapter 8.2 and understood MSMC2DDRbridge have inline ECC support for LPDDR4. According to same tried to implement and have raised following question,

    https://e2e.ti.com/support/processors/f/791/t/925638?tisearch=e2e-sitesearch&keymatch=%20user%3A433302

    Next, i am trying to build test application which is their in PDK, but am failed to find the function implementations in PDK. 

    Thanks for support

    Vaibhav

  • 0 in reply to Vaibhav Kange
    TI__Mastermind 23125 points

    Vaibhav, 

    By "function implementations" are you referring to documentation or test code? The code I referred in the PDK are at:

        \pdk_jacinto_07_00_00\packages\ti\csl\example\ecc\ecc_test_app

    you can build the test for either R5 or A53. 

    Unfortunately, documentation on CSL test programs are thin. But the source code are typically small, standalone and self-explanatory. Please give a try and let me know if you run into any build issues. 

    I will go ahead close the other two ECC threads we communicated earlier, as your now focus on MSMC and DDR. 

    regards

    Jian

  • 0 in reply to jian35385
    Prodigy 100 points
    We have build for R5 and executed the mentioned test example for DDR ECC and observed
    1. For 1 bit ECC error, interrupt is getting generated and respective handler called.
    2. For 2 bit ECC error, when test case tried to read data from test address, it generates abort instead of interrupt.
    Request you to put some pointers if above behavior for 2 bit error is correct or not.
  • 0 in reply to Vaibhav Kange
    TI__Mastermind 23125 points

    Vaibhav, 

    This is the expected behavior as the double bit error was not corrected and processor would be in an unknown state and reset is required. 

    regards

    Jian