Part Number: PROCESSOR-SDK-DRA8X-TDA4X
As per earlier inputs from JIan, I have more points to share where we have
1. MSMC3 RAM (In line ECC support): stored boot, startup code
2. LPDDR4 memory: Interfaced via DDRSS0 which has inline ECC support : stored all data and code
Here, i am still exploring how do i configure following from R5F MCU domain
1. MSMC3 for ECC and
2. LPDDR4 for ECC
3. I understood that, above two modules will generate separate interrupt for ECC and i have to route it through VIM to MCU domain. Is it correct?
4. If i want ECC for just two modules mentioned above, does ECC aggregator module will come into picture?
5. If I want to enable ECC for LPDDR4 and i am using gel file to flash my code then do i need to modify gel file to make ECC feature enable during program flash?. As i understood ECC bytes must be written along with program in LPDDR4( SDRAM).
6. How to test it: I have found some test code in SDK for EMIF ECC testing, I think i have to intialize EMIF in GEL file (documents suggest that it is there in GEL or SBL but i didnt found it). Another is how do it test when my test app is in MCU domain and i cant access EMIF again when test app is running.
Thanks
Vaibhav
