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PROCESSOR-SDK-DRA8X-TDA4X: ECC implementation for cache and TCM

Vaibhav Kange
Prodigy 100 points
Part Number: PROCESSOR-SDK-DRA8X-TDA4X


Hi, We are trying to implement ECC on cache and TCM.

1. For cache,

From TRM it is understood that 1 bit error is correctable and processor will use ECC to correct the bit and generate abort if enabled.

For 2 bit error is uncorrectable and generate abort, Where Application has to take action.

2. For TCM,

From TRM it is understood that TCM needs to be enabled and region have to be configured. By default it is 32 bit aligned for ECC calculation and on SET it is 64 bit.

Again 1 bit correctable error is handled by processor and 2 bit have to handle to processor application.

3. Also, There is DDR3 RAM where want to implement ECC where we currently we store our code. But we dont find any configuration to set up ECC on it.

So we want to confirm our understanding is correct regarding ECC. 

Any help is appreciated

-Vaibhav Kange

  • 0
    TI__Mastermind 23125 points

    Vaibhav, 

    I can confirm your understanding is right with a few minor clarifications:

    1. For cache, i assume you are referring to L1D and L1P of R5FSS - they both support SECDED, thus single bit will be corrected and double bit error is detected as interrupt and error event;

    2. you understanding of ECC quanta is correct. 

    3. For DDR, the device does not support DDR3. it only support LPDDR4, and you can enable in-line ECC optionally. So ECC codes will be stored in addition to the data in the LPDDR memory and there are bandwidth and storage penalties enabling ECC. 

    Please chime back if you have additional questions the ticket will reopen. 

    regards

    Jian

  • 0 in reply to jian35385
    Prodigy 100 points

    Hi Jian,

    Thanks for crisp response. So i am going ahead for further understanding to implement ECC.

    As per your inputs I have more points to share 

    1. MSMC3 RAM (In line ECC support): stored boot, startup code

    2. LPDDR4 memory: Interfaced via DDRSS0 which has inline ECC support : stored all data and code

    Here, i am still exploring how do i configure following from R5F MCU domain

    1. MSMC3 for ECC and

    2. LPDDR4 for ECC

    3. I understood that, above two modules will generate separate interrupt for ECC and i have to route it through VIM to MCU domain. Is it correct?

    4. If i want ECC for just two modules mentioned above, does ECC aggregator module will come into picture?

    Regards

    Vaibhav

  • 0 in reply to Vaibhav Kange
    Prodigy 100 points

    Adding 5th point to earlier questions,

    5. If I want to enable ECC for LPDDR4 and i am using gel file to flash my code then do i need to modify gel file to make ECC feature enable during program flash?. As i understood ECC bytes must be written along with program in LPDDR4( SDRAM). 

    Thanks in advance

    Vaibhav

  • 0 in reply to Vaibhav Kange
    TI__Mastermind 23125 points

    addressed in later thread of:

    https://e2e.ti.com/support/processors/f/791/t/925526

    close this one. 

    Jian