SRIO can not send packets

jie deng1

In my design there are two c6678 DSPs and a FPGA connect to a RapidIO SWITCH , the switch is from IDT and supports Level I and Level II rate up to 6.25G. All of them are configured to work at 4x mode, but the connection is not stable , sometimes the DSP can not send packets( maintaince or DIO) , a read to SP0_ERR_STAT shows that retry or input_error_stopped or output_error_stopped bits are set. The situation seems to be the same when working at 1.25G/2.5G/3.125G , but when configured to work at 5G , the PORT_OK bit in the SWITCH is not set (DSP is OK) and we cann't send packets .Here is my configuration:

// SRIO_SERDES_CFGPLL = rate | 0x00000201; // 1.25、2.5、3.125G
SRIO_SERDES_CFGPLL = rate | 0x00000001; // 5G

SRIO_SERDES_CFGRX0_CNTL = 0x00440495; // Fully adaptive equalization, Half rate, Enable Receiver0
SRIO_SERDES_CFGRX1_CNTL = 0x00440495; // Fully adaptive equalization, Half rate, Enable Receiver1
SRIO_SERDES_CFGRX2_CNTL = 0x00440495; // Fully adaptive equalization, Half rate, Enable Receiver2
SRIO_SERDES_CFGRX3_CNTL = 0x00440495; // Fully adaptive equalization, Half rate, Enable Receiver3

SRIO_SERDES_CFGTX0_CNTL = 0X00180795; // Half rate, Enable Transmitter0
SRIO_SERDES_CFGTX1_CNTL = 0X00080795; // Half rate, Enable Transmitter1
SRIO_SERDES_CFGTX2_CNTL = 0X00080795; // Half rate, Enable Transmitter2
SRIO_SERDES_CFGTX3_CNTL = 0X00080795; // Half rate, Enable Transmitter3

I have tried many other opporaches , changed the PRE_TAP & POST_TAP value , TX SWING , try to disable RX EQ , but it doesn't work as well...

Is there any way to solve the problem, do I need to do some other configure for high speed transmission?

Many Thanks

over 12 years ago

0 tscheck over 12 years ago

TI__Mastermind 23525 points

Here are other posts of potential interest to your case. But I can guarantee your SRIO_SERDES_CFGPLL settings are not correct, i.e. your MPY setting is 0x00, which is reserved. Not sure what your refclk frequency is, but you'll need to consult the SRIO userguide on the appropriate settings.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/196080/850001.aspx#850001 - VMIN setting

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/170264/752157.aspx#752157 - Software error recovery

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/255031.aspx - Refclk port_ok discussions, VRANGE, MSYNC Serdes settings

Regards,

Travis

0 jie deng1 over 12 years ago in reply to tscheck

Prodigy 20 points

The pll setting is correct. I didn't make it clear in the code I posted above. The clock is 156.25M and SRIO_SERDES_CFGPLL=0x251, MPY=10 for 3.125G.

I''ve already changed the VRANGE and MSYNC settings in my design. VRANGE= 0 for 5G half rate and 1 for 3.125G half rate , but it doesn't work.

I set VMIN =15 , the connection seems to be better now, but we still send packets sometimes, I'll try software recovery later.

thanks,

dengjie

0 tscheck over 12 years ago in reply to jie deng1

TI__Mastermind 23525 points

Dengjie,

Ok, good to know about the PLL multiply. It wasn't clear from your code snippet. Sounds like you are on the right track there.

Check out the error registers (SP(n)_ERR_STAT, SP(n)_ERR_DET, etc) for any clues and you can use the gel I referenced in the other post.

If you are not getting port_ok, or it is flakey, it is something physical related. I'm guessing it is reference clock related as in the other post I referenced above. Could also be signal integrity/board related.

Good luck and let me know what you find.

Regards,

Travis

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SRIO can not send packets