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C6678 SRIO does not working with high speed 3.125G 5G

Yang Yang2
Prodigy 30 points
Other Parts Discussed in Thread: CDCE62005

Hi, All

My board have two C6678 communicate with a switch, It is working OK in 1.25G and 2.5G(4x mode), but it does not work with high speed (3.125G and 5G).The Port_OK bit is always 0 when  I read SPn_ERR_STAT Register. My refclk is 156.25Mhz, the basic configuration of the register is as following(3.125G):

        SRIO_SERDES_CFGPLL: 0x051                    //pllMpy= 10;

        SRIO_SERDES_CFGRX[0]:0x440495           //rate =2b'01

        SRIO_SERDES_CFGRX[1]:0x440495

        SRIO_SERDES_CFGRX[2]:0x440495

        SRIO_SERDES_CFGRX[3]:0x440495

        SRIO_SERDES_CFGTX[0]:0x180795

        SRIO_SERDES_CFGTX[1]:0x080795

        SRIO_SERDES_CFGTX[2]:0x080795

        SRIO_SERDES_CFGTX[3]:0x080795

       Is there any way to solve the problem, do I need to do some other configure for high speed transmission?

       Many Thanks

Yang

  • 0
    Prodigy 70 points

    Hi,

      I have  the same question,  I have no idea of whether it is the problem of dsp6678 or the switch.

    if the switch is ok, does any other configuration should be config when  setting the srio speed as 3.125Gbps and 5Gbps???

    Thanks

  • 0
    TI__Mastermind 23525 points

    The Vrange (bit 9 of CFGPLL) needs to be set high...

    If LINERATE × RATESCALE < 2.17GHz, VRANGE should be set high.

    Also, what is your configuration, i.e. 4 ports of 1x, 1port 4x, etc?  If you are in any mode other than 4 ports 1x, you will need MSYNC (bit 20 of SRIO_SERDES_CFGTX) set on one or more lanes.

    What is the value of the SRIO_SERDES_RSVD register? 

    Hope that helps,

    Travis

  • 0 in reply to tscheck
    Prodigy 30 points

    Hi Travis,

          I use 1port 4x mode, I have tried the configuration you suggested, now I configure the registers as following:

             SRIO_SERDES_CFGPLL: 0x251                    //pllMpy= 10; VRANGE =1

            SRIO_SERDES_CFGRXn:0x440495           //rate =2b'01, MSYNC =1

            SRIO_SERDES_CFGTXn:0x180795

         But it still do not working in 3.125G and 5G.

         I can't find the SRIO_SERDES_RSVD register in the SRIO user guide( this register appears only once in page 2-10). How can I configure it?

         I hope this will not be my PCB layout problem, I have limited the prop delay within 10mil.

         Thanks

    Yang

  • 0 in reply to Yang Yang2
    TI__Mastermind 23525 points

    Vrange looks correct now.  Just to confirm on the MSYNC too, your original settings were correct for 1 port 4x mode, i.e. only the MSYNC for lane 0 should be high.  Hopefully you didn't change it for all the lanes.  I'll have to look to see if SRIO_SERDES_RSVD is actually accessible or not.  For your port configuration, it won't matter anyway.  So from what I can tell your Serdes settings are correct.  The only other thing I can think of is that maybe your port_ok is toggling in and out.  Please take a look at this suggestion and let me know if that helps. 

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/196080/850001.aspx#850001

    If you still can't get port_ok, then it is something physical, i.e. board, refclk frequency offset/jitter from the DSP SRIO and switch SRIO point of view.

    Regards,

    Travis

  • 0 in reply to tscheck
    Prodigy 30 points

    Hello Travis,

            Thanks for you help. Our SRIO works ok on 5G now, the problem is our refclk, we reconfigure the setting of cdce62005. It is working fine! 

           Regards,

    Yang Yang