TMDSEVM6670 Manual memory initialization. Does it even work?

Hi,

pcieboot_ddrinit test code is used for initialize the DDR memory on PCIe boot mode, this code use the standard platform lib driver codes/functions. For more information refer PCIe boot linux host loader demo code(pciedemo.c).

Are you getting different delay values for platform_delay() function on debug mode test and on-board run test?

Thanks,

I guess i should explain more details.

F.E., i have 2 functions - "platform_init", which is a standart platform lib function i can't step into and trace the execution, and "platform_initialization", which is written by me, but that's a full copy of "platform_init", i made it to step-by-step tracing execution. And i've inserted the most functions into program text, due to easy tracing process. When i launch program, with using standart library functions, i recieve the correct register and delay values. And, for some reason, using "handmade" functions leading to correct register, but incorrect delay values.
After that, i've tryed to load both programs through ethernet, to initialize DDR. Both of them load correctly, and when, after that, i'm loading program in DDR, which also uses delay, it works correctly after both kind of initialization. I was ok to me, but now it's very important to me to make the "handmade" program work correctly.

Hi,

Please share your handmade platform_initialization code, i will try to reproduce your issue on my setup.

Thanks,

This code is included in the project, attached in my first message.

Could you please tell about any news of my question? I still couldn't achieve my desired results alone.

For some reason, PLL can't initialize during the:

#ifdef PLATFORM_PLL_REINIT
    for (loop_count = 0; loop_count < 10; loop_count++) {
        platform_errno = 0;
#endif
/* here lies the function code */

 platform_init_return_code = loop_count;

    if (loop_count == 10) {
        platform_errno = PLATFORM_ERRNO_GENERIC;
        return ( (Platform_STATUS) Platform_EFAIL);
    }
}

section. For some reason, i have console output:

[C66xx_0] SYSCLK/ALTCORECLK is the input to the PA PLL...
[C66xx_0] PA PLL programmable multiplier = 32
[C66xx_0] PA PLL programmable divider = 2
[C66xx_0] PLL3 Setup for PASSCLK @ 1966.1 MHz...
[C66xx_0] PLL3 Setup... Done.
[C66xx_0] DDR3 PLL programmable multiplier = 20
[C66xx_0] DDR3 PLL programmable divider = 1
[C66xx_0] PLL2 Setup... Done.

which repeat 10 times, and then throws an error and platform initialization fails. This is happening, when i'm using custom board with TMS320C6670 processor. The custom board fully repeats the hardware structure of the evaluation board TMDSEVM6670. Just FYI

Ok, that's good, it helped me in tracking evaluation board code and fix some mistakes. But i still need explanations, why PLL frequencies can't be established during pll init section, described in my project. Why are boards with same process and architecture performing so different?

UPD.

When i reach 271 line in the evmc6670.c

PLLCTL_REG |= (1 << 0);
Program stops, and throws me this:
C66xx_0: Trouble Reading PC Register: (Error -1178 @ 0x6E) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
C66xx_0: Trouble Reading Register ControlRegisters_CSR: (Error -1178 @ 0x41) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
C66xx_0: Trouble Reading Register ControlRegisters_CSR: (Error -1178 @ 0x41) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
C66xx_0: Trouble Reading Memory Block at 0x1840020 on Page 0 of Length 0x4: (Error -1178 @ 0x1840020) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
C66xx_0: Trouble Reading Memory Block at 0x1840040 on Page 0 of Length 0x4: (Error -1178 @ 0x1840040) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
C66xx_0: Trouble Reading Memory Block at 0x1840000 on Page 0 of Length 0x4: (Error -1178 @ 0x1840000) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
C66xx_0: Trouble Reading Register ControlRegisters_DNUM: (Error -1178 @ 0x50) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
C66xx_0: Trouble Reading Memory Block at 0x1840020 on Page 0 of Length 0x4: (Error -1178 @ 0x1840020) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
C66xx_0: Trouble Reading Memory Block at 0x1840040 on Page 0 of Length 0x4: (Error -1178 @ 0x1840040) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
C66xx_0: Trouble Reading Memory Block at 0x1840000 on Page 0 of Length 0x4: (Error -1178 @ 0x1840000) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
C66xx_0: Trouble Reading Register ControlRegisters_DNUM: (Error -1178 @ 0x50) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
C66xx_0: Trouble Reading Register ControlRegisters_CSR: (Error -1178 @ 0x41) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
C66xx_0: Trouble Reading Memory Block at 0x10832238 on Page 0 of Length 0x4: (Error -1178 @ 0x10832238) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
C66xx_0: Trouble Reading Memory Block at 0x2310100 on Page 0 of Length 0x100: (Error -1178 @ 0x2310100) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)


What is this? Why this is happening? Where i should search for an issue?

Dear Taras,
Do you want to reinitialize or initialize the PLL in your code ?
Like changing the core frequency ?
Can you attach your project ?

Hello Titus.

Now i want to initialize pll in my code, without changing frequency. I have coreclock value = 122,88 MHz and i want to recieve 999,98 MHz at the exit.
Here's my project:   https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/6138.pcieboot_5F00_ddrinit.7z