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Linux/AM5728: PCIe EP device not recognized

yongjun wang
Intellectual 725 points
Part Number: AM5728
Other Parts Discussed in Thread: TMS320DM8168

Tool/software: Linux

Hi ,our custom board based on AM5728 idk referenc.the topology of the pcie as follow figure

we load the ep program before  the system on am5728 boot up, we enter the commond lspci in the consol, the return information just have the the device am5728 and the PXEX8624,there's no infromation about the fpga.the result show as follow picture,

if we replace the am5728 board by the TMS320DM8168 board,the device information can be get correctly.the sdk version is ti-processor-sdk-linux-rt-am57xx-evm-03.03.00.04,the dts about the pcie in the am572x-idk.dts file:

&pcie1_rc {
status = "okay";
};

&pcie1_ep {
};

just remove the "gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;" because we not used. 

do we need some operate to config the kernel? or is there some method to solve this? we searched the issue on the forum,but have no similar link posted. thanks for someone to help us.

  • 0
    TI__Guru 50170 points
    Hi, Yongjun,

    Could you post the output of "lspci -v"? and is it possible to try connect the EP to the board directly without the swtich?

    Rex
  • 0 in reply to Rex Chang
    Intellectual 725 points
    Hi,Rex,because the design the EP must be connected by switch to RC,the lspci -v show as:
    root@am57xx-evm:~# lspci -v
    00:00.0 PCI bridge: Texas Instruments Device 8888 (rev 01) (prog-if 00 [Normal )
    Flags: bus master, fast devsel, latency 0, IRQ 435
    Memory at 20100000 (32-bit, non-prefetchable) [size=1M]
    Memory at 20020000 (32-bit, non-prefetchable) [size=64K]
    Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
    Capabilities: [40] Power Management version 3
    Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+
    Capabilities: [70] Express Root Port (Slot-), MSI 00
    Capabilities: [100] Advanced Error Reporting
    Kernel driver in use: pcieport

    01:00.0 Non-VGA unclassified device: PLX Technology, Inc. PEX 8624 24-lane, 6-P)
    !!! Invalid class 0000 for header type 01
    Flags: fast devsel
    Bus: primary=00, secondary=00, subordinate=00, sec-latency=0
    Capabilities: [40] Power Management version 3
    Capabilities: [48] MSI: Enable- Count=1/4 Maskable+ 64bit+
    Capabilities: [68] Express Upstream Port, MSI 00
    Capabilities: [a4] Subsystem: PLX Technology, Inc. PEX 8624 24-lane, 6-]
  • 0 in reply to yongjun wang
    TI__Guru 50170 points

    Hi, Yongjun,

    The reason for direct connect the EP to AM5728 is to verify AM5728 configuration and exclude any issue may introduced by the switch. I did a search and found there was a smiilar case as yours in the e2e forum. Could you check if it applies to you?

    e2e.ti.com/.../597740

    Rex

  • 0 in reply to Rex Chang
    Intellectual 725 points
    Thanks Rex,we will try by the link you offered tomorrow.and the result will be provided here.
  • 0 in reply to yongjun wang
    Intellectual 725 points

    Hi,Rex,we connect the EP directly,the EP information can be find with the lspci -v,we referenced the link you send us,we have some doubts about the link,
    (1) "The PEX 8606 header type is read from PCI driver probe.c using byte access at 0xe and always gets back 0x00. Changing this to a 32 bit access at 0xc got the correct header type value of 0x01." does it mean modify the 0xe by 0xc.
    (2) "I've modified probe.c in the kernel (4.4.49) to handle this, but suspect there could be other problems due to non aligned access." we couldn't find the the place in the prob.c about (1) to modify.we find int the prob.c line 1187  with red box

    and line 1236 to deal with different hdr_type.,

     we seach the MACRO PCI_HEADER_TYPE are defined in the pci.h under board-support/u-boot-2016.05+gitAUTOINC+4db46a6bbd-g4db46a6bbd/include dir.

    we change the 0x0e to 0x0c ,but the ep cann't be recognized by the RC, did we understand the link wrong?

  • 0 in reply to yongjun wang
    TI__Guru 50170 points
    Hi, Yongjun,

    The way I understand is not only the read address need to be changed from 0x0e to 0x0c, but also the length. Instead of doing byte read, it needs to read a word (32 bits).

    Rex
  • 0 in reply to Rex Chang
    Intellectual 725 points
    Thank you Rex,we plan to read the driver bout pci,and try to understand how to correct this problem.
  • 0 in reply to yongjun wang
    TI__Guru 50170 points
    Hi, Yongjun,

    I have not heard back from you, so I'll close this thread for now. You can always re-open it if it does not solve your problem. If you have other issues, please submit a new one.

    Rex
  • 0 in reply to Rex Chang
    Intellectual 725 points
    Hi Rex,I am sorry about forgetting this. Now we just use the pcie without switch, thank you.
  • 0 in reply to Rex Chang
    Intellectual 725 points

    Hi,Rex,yes you are right ,"The way I understand is not only the read address need to be changed from 0x0e to 0x0c, but also the length. Instead of doing byte read, it needs to read a word (32 bits)." we modify the prob.c in the /home/ti-processor-sdk-linux-rt-am57xx-evm-03.03.00.04/board-support/linux-rt-4.4.41+gitAUTOINC+968d071ce9-g968d071ce9/drivers/pci ,the ep can be emunated now.

    int pci_setup_device(struct pci_dev *dev)
    {
    u32 class;
    u16 cmd;
    //u8 hdr_type;
    u32 hdr_type;
    int pos = 0;
    struct pci_bus_region region;
    struct resource *res;

    //if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
    if (pci_read_config_dword(dev, 0xc, &hdr_type))
    return -EIO;
    hdr_type = hdr_type>>16;
    ...............