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AM6442: About A53 core cache maintenance operations.

tomitama
Expert 1090 points
Part Number: AM6442

I have a question about A53 core cache maintenance operations.

A53 TRM has the following description.
-----
Arm Cortex-A53 MPCore Processor Technical Reference Manual (Revision: r0p4)
4.2.5 AArch64 cache maintenance operations

PoU = Point of Unification. PoU is set by the BROADCASTINNER
signal and can be in the L1 data cache or outside of the processor, in
which case PoU is dependent on the external memory system.

PoC = Point of Coherence. The PoC is always outside of the processor
and is dependent on the external memory system.
-----


Which caches do PoU and PoC refer to in AM6442?
Also, what is the value of "BROADCASTINNER" set?

  • 0
    TI__Mastermind 27050 points
    tomitama said:
    Also, what is the value of "BROADCASTINNER" set?

    On AM64x family of devices BROADCASTINNER is 0. Which means PoU is inside the dual A53 cluster caches (L2 cache). There is still the option to implement cache coherent IO transactions via the ACP port using initiators like DMA with ASEL set to 14 or 15. This is utilized by Linux Ethernet for higher performance.

    PoC is the final destination memory. Which means DDR controller for the main memory (the controller has FIFOs and internally reorders DDR accesses coherently). Once the transaction is received by the controller it can be considered to have landed at the PoC. Similarly the OCRAM is the PoC. The rest of the onchip memories should not be typically configured as cacheable by A53.

    See the ARMv8 programmers guide for a description on PoU and PoC that complements the TRM and the above.

    https://developer.arm.com/documentation/den0024/a/Preface

      Pekka

  • 0 in reply to Pekka Varis
    Expert 1090 points

    Hello Pekka,
    Thank you for your reply.

    Now that I understand PoU and PoC, Please tell me about the following.

    Does DC CVAC (Data cache clean by VA to PoC) clean the L1 and L2 caches?
    Does DC CVAU (Data cache clean by VA to PoU) clean only the L1 cache?

  • 0 in reply to tomitama
    TI__Mastermind 27050 points

    See for example the AM64x RTOS SDK for example bare metal cache management in C:\ti\psdk_am64x\rtos\pdk_am64x_07_02_01_11\packages\ti\csl\arch\a53\src (if you installed default Windows) file csl_a53v8cache.asm ,

    SW has no direct control over L1 vs L2 caching in the A53 cluster. There are further buffers and structures related to caching and having multiple operations in flight, you should view the A53 cluster as one coherent domain with caches and buffers which the HW manages, there is no need to invalidate to the PoU. The programmers responsibility is limited to barriers (DMB, https://developer.arm.com/documentation/100941/0100/Barriers ) for ordering of transaction to the PoU. Only reason on AM64x A53 to do cache maintenance from SW is for interaction with memory shared with DMA or R5, this is to the PoC and you will need a DSB barrier as is shown in the csl_a53v8cache.asm examples.

    Depending on what you are trying to achieve with SW cache management, see https://e2e.ti.com/support/processors/f/processors-forum/989753/am6442-cache-coherency-with-dma-masters-and-other-processors-r5f-prus for enabling coherency.

      Pekka

  • 0 in reply to Pekka Varis
    Expert 1090 points

    Hello Pekka,
    Thank you for your reply.

    I have two questions.

    -----The first question-----
    About the cache maintenance operation function of AM64x RTOS SDK.
    I don't want to know how to maintain coherency, I want to know the range of cache clearing.

    AM64x RTOS SDK
      csl_a53v8cache.asm

    CSL_a53v8CleanDcacheMvaPoC
      Does the DC CVAC of this function clean the L1 and L2 caches?

    CSL_a53v8CleanDcacheMvaPoU
      Does the DC CVAU of this function clean only the L1 cache?

    -----The second question-----
    About your answer below.

    Pekka said.
    Depending on what you are trying to achieve with SW cache management, see e2e.ti.com/.../am6442-cache-coherency-with-dma-masters-and- other-processors-r5f-prus for enabling coherency.

    I checked the contents of the URL.
    Does AM64x maintain coherence on all R-core, A-core, SRAM, DDR, and DMA access by using ACP?

    AM64x TRM states that ACP is not supported. Can I use ACP?
      AM64x Processors Silicon Revision 1.0 Texas Instruments Families of Products
        6.2.1.2 R5FSS Not Supported Features

    -----

    Best regards.

  • +1 in reply to tomitama
    TI__Mastermind 27050 points
    tomitama said:
    CSL_a53v8CleanDcacheMvaPoC
      Does the DC CVAC of this function clean the L1 and L2 caches?

    Yes this cleans the A53 caches to the backing memory.

    tomitama said:
    CSL_a53v8CleanDcacheMvaPoU
      Does the DC CVAU of this function clean only the L1 cache?

    This is internal to the A53 cleaning to the PoU, will not clean to the backing memory outside the A53 cluster. Other than writing self modifying code that one would want to get pulled into L1I cache later it is not clear to me when this would be useful on an AM6442, the two A53 cores L1D's are kept coherent without the need for SW cache maintenance.

    tomitama said:
    Does AM64x maintain coherence on all R-core, A-core, SRAM, DDR, and DMA access by using ACP?

    As a general approach no. Traffic from DMA and R5 can utilize the ACP port of the A53 by using ASEL values of 14 or 15. In the SDK examples, Linux and Ethernet traffic is the example of using this path.

    tomitama said:
    AM64x TRM states that ACP is not supported. Can I use ACP?
      AM64x Processors Silicon Revision 1.0 Texas Instruments Families of Products
        6.2.1.2 R5FSS Not Supported Features

    The A53 cluster supports the ACP to keep the A53 caches coherent, see TRM section "6.1.3.2 Arm Cortex-A53 Cluster". The R5's do not, see TRM section "6.2.1.2 R5FSS Not Supported Features". The R5 must use SW managed caches coherency for regions marked cached in its MPU.

      Pekka