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AM6442: About enabling A53 core cache.

tomitama
Expert 1090 points
Part Number: AM6442

I am investigating the cache enable setting of the A53 core.

When I set the System Control Register as shown below, I was able to confirm that the L1 instruction cache was valid, but it seemed that the instructions were not cached in the L2 integrated cache.
Do I have to enable the MMU to cache instructions in the L2 integrated cache?

-- Set value ------
SCTLR (System Control Register)
[12] I: 1 (Instruction caches enabled.)
[02] C: 1 (Enables data and unified caches.)
[00] M: 0 (Disables MMU.)
-------------------

Also, is there a way to use the entire L2 integrated cache as a data cache when the instruction cache is enabled?

  • 0
    TI__Mastermind 27050 points

    Hi,

    If your goal is to write your own bare metal test code for A53 let me suggest to look at https://developer.arm.com/documentation/dai0527/a/ as a guide to write minimal A53 (or any ARMv8) initialization code.

    tomitama said:
    When I set the System Control Register as shown below, I was able to confirm that the L1 instruction cache was valid, but it seemed that the instructions were not cached in the L2 integrated cache.

    I'm not sure how you verified that the L2 did not contain the instruction and only L1 instruction did. The A53 instruction allocation policy is "tends-towards-inclusive instruction allocation policy", which usually means the instruction is allocated in both caches. Later the L1 entry might get evicted but the L2 entry might still be there. In general with A53 (and ARMv8-A) the caching is treated as one block, there is no fine grained control over the levels of caching per page (region of memory).

    tomitama said:
    Do I have to enable the MMU to cache instructions in the L2 integrated cache?

    In general MMU has to be enabled for cache to work as the page table entry gives the cacheability and other attributes for the memory region. For custom bare metal code I suggest to look at ARMv8 documentation like https://developer.arm.com/documentation/dai0527/a/ section 5.3 Configuring the MMU and caches.

    tomitama said:
    Also, is there a way to use the entire L2 integrated cache as a data cache when the instruction cache is enabled?

    No, A53 L2 is a unified cache.

      Pekka

  • 0 in reply to Pekka Varis
    Expert 1090 points

    Hello Pekka,
    Thank you for your reply.

    I have one question.

    　Pekka said.

    　In general MMU has to be enabled for cache to work as the page table entry gives the cacheability and other attributes for the memory region. 

    Does this mean that SCTLR's C [2] and M [0] must be enabled for the L2 integrated cache to cache the instructions?

    Best regards.

  • +1 in reply to tomitama
    TI__Mastermind 27050 points

    Yes, the C bit is data and unified cache enablement in A53. L2 cache is a unified cache.

    Usage of SCTRL is documented in https://developer.arm.com/documentation/dai0527/a/  :

    // Enable caches and the MMU.
    MRC P15, 0, R1, C1, C0, 0 // Read SCTLR.
    ORR R1, R1, #(0x1 << 2) // The C bit (data cache).
    ORR R1, R1, #(0x1 << 12) // The I bit (instruction cache).
    ORR R1, R1, #0x1 // The M bit (MMU).
    MCR P15, 0, R1, C1, C0, 0 // Write SCTLR.
    DSB
    ISB