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DAC38RF89: SYSREF INPUT, Fixed VOL Input Bias Setup for AC Coupled Network

Part Number: DAC38RF89
Other Parts Discussed in Thread: LMK04828, DAC38RF83

Hi, 

I am referencing section 7.4 on page 14 of this document: 

https://www.ti.com/lit/an/slaa696/slaa696.pdf?ts=1600379502443&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FDAC38J84&_ticdt=MTYyNTA5MjU4NnwwMTY0Y2M1MWQ1ZmQwMDE5YTljMTczNmE5Mjc1MDMwNzIwMDI1MDZhMDBiZDB8R0ExLjIuMTExMDYyMTMwMi4xNTMyNDM2Mjc0fDA 

It mentions using a network with 1150ohm pullup on SYSREF+ and 453 pulldown on SYSREF- to create a fixed VOL for times when SYSREF is not driven. 

I wanted to confirm, isn't this backwards? If you are pulling SYSREF+ up and you are pulling SYSREF- down, wouldn't this create a VOH scenario with a positive differential voltage across the inputs from + to -? Wouldn't this leave the SYSREF input as "asserted" or logic high? Why would the reverse not be done, with SYSREF- pulled above SYSREF+ to leave the SYSREF differential input biased in the logic low, or unasserted state with a negative differential voltage across the inputs from + to -?

I have setup with driver with ~2.2V Common mode and ~0.75V to 1.2V differential swing for SYSREF so I believe AC coupled approach is necessary as resistor divider to bring the common mode down to 0.5V (the SYSREF input common mode spec for the DAC38RF89) would cause too much signal attentuation

  • Hi Steven,

    You are correct. I made a mistake on this one. This should be VOH. See below for TINA Simulation result. 

     SYSREF - autosave 15-12-31 09_24.TSC

  • Thanks Kang. I see that your simulation biases the input to the "High" or "1" state when the input isn't driven such that Vreceiver_p is ~100mV above Vreceiver_n. 

    However, I am still not understanding WHY we would want the inputs to be biased to this state rather than the opposite state? Wouldn't we want a logical low on the inputs when the SYSREF driver is idling in the "Low" state or when the inputs are not driven?

    In your simulation, the first 100us have Vdriver_n at ~2.2V and Vdriver_p at ~1.25V which means the SYSREF driver is LOW, SYSREF is unasserted by the driver. During this time, Vreceiver_p is ~100mV above Vreceiver_n which I believe means SYSREF would be seen as HIGH at the receiver. Isn't this the opposite of what we want in this case? 

    Please do correct me if I am mistaken anywhere. 

  • Hi Steve,

    the goal is to make sure during SYSREF driver idle state the SYSREF receiver is not set to metastable state of "0V" differential. Either logic low or logic hi is fine at the SYSREF receiver side when the SYSREF driver is in idle state. 

    In your simulation, the first 100us have Vdriver_n at ~2.2V and Vdriver_p at ~1.25V which means the SYSREF driver is LOW, SYSREF is unasserted by the driver. During this time, Vreceiver_p is ~100mV above Vreceiver_n which I believe means SYSREF would be seen as HIGH at the receiver. Isn't this the opposite of what we want in this case? 

    The situation above is specific to the LMK04828 driver where the SYSREF driver idles at logic low. Yes, I would recommend the SYSREF receiver also set to logic low in this case. You will need to double check your SYSREF driver's idle state whether it is in logic HI or logic low.

    Ultimately, the SYSREF receiver registers the "rising edge" of the SYSREF. The DAC38RF83 has programming registers to enable when the logic wants to start registering the SYSREF pulses. You can wait for the SYSREF to stabilize and then enable the programming registers to register the SYSREF pulses.