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AFE7950EVM: Internal ADC and DAC Clock

Part Number: AFE7950EVM
Other Parts Discussed in Thread: AFE7900EVM

How do you configure the AFE7950EVM or AFE7900EVM to generate both the DAC and ADC clock internally (DACFs = 7500 MHz, ADCFs = 2500 MHz)?

  • Hi Travian,

    To adjust the DAC and ADC sampling clocks you can adjust the Fadc and Fdac parameters in your Latte script and you can adjust the decimation and interpolation factors to get the required lane rate. One thing to note is that depending on the clock distribution method, 3 methods are shown in the picture below, you may be limited to certain sampling rates. 

    The AFE79xxEVMs have an onboard 122.88MHz crystal that is used to generate the ref frequency, 491.52MHz, to the AFE and this limits the sampling clocks to factors of 122.88. If you would like to sample at exactly 2500MHz and 7500MHz you can use an external 1GHz clock to the LMK and this would provide a 500MHz clock to the AFE, which can be used to generate the 2.5G and 7.5G sampling clocks. The picture below shows the changes required in the Latte scripts in order to use the two methods that I have mentioned.

    Regards,

    David Chaparro 

  • Hey David!

    Thanks for your response. Which connector do you connect the 1 GHz external reference to?

  • Hi Travian,

    The 1GHz external reference has to be connected to J14, LMK_CLK_IN, and I usually set the power level to about 10dBm.

    Regards,

    David Chaparro 

  • Hey David,

    I was able to setup the 1 GHz reference, however, I am not able to get the Latte script to work. Are you able to update the S1_OnboardClk_RX_250M_TX_FB_500M.py file in order to provide 500MHz clock to the AFE? Is there a way to use 50 Mhz instead of 1G external clock?

  • Hi Travian,

    I will take this offline and provide an updated script through email.

    Regards,

    David Chaparro