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AFE7950EVM: usage / integration guide for use with Xilinx VPK12O EVM (Versal)

Part Number: AFE7950EVM

All,

The project I'm working on requires we use an Xilinx VPK120 EVM, this uses the newer Xilinx Versal FPGA.

1) has the AFE7950EVM been integrated with a Versal Premium FPGA or better still this board?

2a) if so, is the software / FPGA design design available?

2b) if not, is there an outline of the changes required to migrate from a ZCU106 to a VPK120?

https://www.xilinx.com/products/boards-and-kits/vpk120.html

Andrew.

  • Hi Andrew,

    We are currently developing support for Versal in the TI JESD204c IP. This is expected to be released by early 2Q. Unfortunately, until then we won’t have a migration path for existing reference designs, because Versal enforces a block design based approach for integrating transceivers. This is different from the existing integration methodology of the TI IP. 

    Regards,

    Ameet 

  • Ameet, 

    Thank you for the swift response.

    That's great news. I look forward to an early Q2 release.

    If the beta / pre-release code is available before then, we would happy to assist where possible..

    Is the VPK120 the targeted Versal platform?

    Andrew

  • Hi Andrew,

    The targeted platform for HW validation is the VCK190. We don’t have a beta release yet, because the Versal infrastructure has enforced a rework of the TI JESD IP architecture (the transceiver can no longer be embedded within the IP, as it can only be instantiated in a BD). 

    Regards,

    Ameet