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Original question:

DAC38RF82EVM: LMFSHd = 82380 setting on the GUI

DAC38RF82: JESD_PHASE_MODE

Kazuhiko Hirano
Genius 15458 points
Part Number: DAC38RF82


Hello,

My customer would like to know for what the JESD_PHASE_MODE bits of the JESD Lane Enable Register.
Please elaborate.
And in case of the Wideband-DUC mode with LMFSHd = 82380, what should those bits be set?

Best regards,

K.Hirano

  • +1
    TI__Expert 5055 points

    Hi K.Hirano

    In order to minimize clock spurs the lane clock used in the JESD RX clock will be made up of multiple phases. Depending on the mode, you would need to change the JESD_PHASE_MODE bits to have 1, 2, 4 or 8 clock phases available.

    In table 41 of the datasheet, the column titled “CLOCK PHASES (1-0)” shows the value for each of the different modes based on the interpolation value. So, for the 82380 LMFS mode you would set the JESD_PHASE_MODE bits to 00 if you are using an interpolation value of 1 or 2.

    Best,

    Camilo