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AFE7799 alarm check issue

Other Parts Discussed in Thread: AFE7799, AFE7769EVM, AFE7769

Hi

We read and check AFE7799 alarm after initiallization and get error message...
JESD 204B: 8b/10b disparty error.
JESD 204B: 8b/10b not-in-table code error.
code synchronization error.
link configuration error.

But, in this moment, AFE7799 can transmit and receive signal.

How can i debug all error state to make sure alarm check is workable?

Alarm register infor
API process get from TI.
Register Read..
164h, 165h, 166h & 167h for 8 lanes.

 

  • Kevin replied to customer via email but pasting his response the keep the record in E2E too.

    Can you please use clearJesdRxAlarms(int fd) API to clear the alarm and then read it again? Also, to verify the link is good.  Can you use the readEye commands(see attachment) to read the eye margin value. 

    If the link is good, the outputs should be non-zero or f0 values.  In the screenshot below, the readouts on the left were taken when the link was bad, the one on the right is when the link is good.

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/220/3515.serdes-eye-read-commands

  • Hi Kevin & Allan,

    I replied our result in email to both E2E forum and here, since we had an email last time.

    According to TI suggestions, I place TI APIs before our current JESD Status Check mechanism. As shown in picture, all error messages are literally cleared after clearJesdRxAlarms() executed.


    With next picture,  there are several new questions:

    1. There are GPIO reset related messages on the right screen, which means that our JESD Status Check mechanism found JESD init failure, however, either getJesdRxAlarms() and getJesdRxLinkStatus() seems not report any difference.
    1. As defined in c, getJesdRxLinkStatus() returns value in 4 bits. But I always have “10” as return value, which is “1010” in binary.
    2. I read register 0x4660, 0x4661 for eye margin value, but its always “0”. Should we read eye margin value during data transmitting? Our current JESD Status Check mechanism does not transmit any signal when it executes.
    3. I asked definitions of ftdi_writeReg(), ftdi_readReg() in another thread:  AFE7799: JESD204B Link Fail, and still wait for response.

  • Michael,

    If i understood what you said correctly.

    1. clearJesdRxAlarms() API worked

    2. Even though JESD status check mechanism indicates there is JESD init failure, but using the getJesdRxAlarms() , it always returns 1010, if the getJesdRxAlarms() API works as expected, it should output either 0 or 1, not 2.  However, I tried the getJesdRxLinkStatus API on our EVM this afternoon.  The function seems to be working fine.  When the link was up, the function output 10, when i disconnected the FPGA from the AFE7769EVM, function output 0.

    3. On the FPGA that we are using, once the link between FPGA and AFE has been established, FPGA will automatically start sending 0s to the AFE.  

    Eye margin values when FPGA is transmitting 0s:

    Eye margin values when FPGA is transmitting a CW tone(-10dBFs):

    4. We use APIs to check the things that were mentioned AFE7799: JESD204B Link Fail thread.  To check if AFE Tx is working or not, txSigGenTone API can be used to generate an internal tone from AFE to see if there is any Tx output on the spectrum analyzer.  In addition, ADC to DAC loopback commands can be used to see if Rx and Tx are working or not.  See link below for the loopback commands.  To use the commands, a signal generator is needed to input a CW tone to RxA.  If AFE7769 is functional, an output should be observed on TxA

     ADC to DAC loopback commands:

     /cfs-file/__key/communityserver-discussions-components-files/220/ADC-to-DAC-loopback-commands.txt

  • Hi Kevin,

    Thanks for your rapid response. You made correct understanding, let me ask a little further:

    2. I think it is just typo, that you misplaced getJesdRxLinkStatus() with getJesdRxAlarms(). If I understand your test result correctly, getJesdRxLinkStatus() does return "10"  as 2 in binary, not in decimal 0, 1 or 2 ?

    3. This is an important information for us. Much appreciated.

    4. We will discuss about using internal tone and ADC to DAC loopback commands to check the link between FPGA and AFE ASAP. It is also an important information, thank you. But In my original question, I asked the definition of ftdi_writeReg() and ftdi_readReg(), I need these two for TI's AFE77xx_RegWrite() and AFE77xx_RegRead(). What we are using is our own way to read or write TI's register, we wish to have a decent way to do this. Please kindly offer it to us.

  • 2. The output 10 is in decimal, in binary, it is 1010, 10 binary in decimal is 2.  According to the definition provided in the AFE77xxKeyCFunctions_v1p12 txt file, 2 means link is up.  1010 means the link is up for both top 4 and bottom 4 lanes.

    4. ftdi_writeReg() and ftdi_readReg()  are commands to read and write values into the registers.  Alphanetworks can implement the AFE77xx_RegWrite and AFE77xx_RegRead functions to achieve these tasks.