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Original question:

AFE7900EVM: AFE7900EVM configuration from external Python script (outside the Latte)

AFE7900EVM: Decimation factor vs JESD204 setup

Tomas Svoboda
Prodigy 59 points
Part Number: AFE7900EVM


Dear support,

Currently, I am working with the reference design for the ZCU102 board, which has the following parameters:

FPGA side (8 lanes shoud be implemented):

Latte side (ADC and LMK): Here's the link to the script. I'm unable to insert it directly here: TI_IP_12Gbps_8Lane_ConfigLmk.py 

1) What is my intended goal

I need to set the decimation factor for the ADC to a value of DDC = 48. In this case, I'm getting a failure message in Latté that says 'ADC Serdes TX Lane Rate not in Serdes Range. Lane Rate: 1013.76.' This probably means a low lane rate. If I understand correctly, it will be necessary to use a mode with only four lanes, is that correct? What needs to be modified for this setting (in the Latté script and on the FPGA side).

And secondly, what will be the sample format in a different mode? i.e. 4 channels mapped onto a) 1 lane, b) 2 lanes?

2) Additional question

The reference design uses 8 lanes, so why is the script set to: sysParams.LMFSHdRx=['44210', '44210', '44210', '44210'], which should mean 4 lanes?

Thanks in advance for your support!

Best regards,

Tomas 

  • 0
    TI__Genius 10875 points

    Hi Tomas,

    1. There are two TI JESD204 IP reference designs for AFE79xxEVM + ZCU102 in AFE79xx secure folder. One design uses 8b/10b encoding with SERDES lane rate ~10Gbps and the other uses 64b/66b encoding with SERDES lane rate ~12Gbps. I see that you are using the second one. As your goal is to use decimation 48, SERDES lane rate will be lower than 6Gbps. 8b/10b encoding should be used in this case. Please use the 8b/10b design as a starting point. For more details on this refer to Table 4-2 in this app note: https://www.ti.com/lit/an/sbaa402a/sbaa402a.pdf 

    With decimation factor 48, using 2 lanes, lane rate will be ~5Gbps. 

    2. LMFSHdRx parameters are given for 2 Rx channels in the scripts. So '44210' means 4 lanes for 2 channels. Which is 8 lanes for all 4 Rx channels. To use only 2 lanes as I mentioned above, set LMFSHdRx parameters to '14810'

    Regards,

    Vijay

  • 0 in reply to Vijayendra Varma Siddamsetty
    Prodigy 59 points

    Hi Vijay,

    thanks for your fast response!

    Okay, the steps could be as follows:

    1) Latte side: update the setupParams.fpgaRefClk , sysParams.LMFSHdRx  and sysParams.ddcFactorRx 
    2) FPGA side: update transceiver IP for 2 lane and appropriate larate (and reference clock), update sys_clck generated by PLL and remap data.


    What is the data format of the output from JESD204 IP? If I have 2 lanes, but 4 channels, each with 2x16 IQ pairs, what would be the format of each frame?

    Thansk a lot.

    Tomas 

  • 0 in reply to Tomas Svoboda
    TI__Genius 10875 points

    Hi Tomas,

    When using 2 lanes for 4 channels i.e. 4 IQ channel pairs, frame format is as shown below: 

    TX 28810
    Octet 1 2 3 4 5 6 7 8
    Lane 1 TX1_i0[15:0] TX1_q0[15:0] TX2_i0[15:0] TX2_q0[15:0]
    Lane 2 TX3_i0[15:0] TX3_q0[15:0] TX4_i0[15:0] TX4_q0[15:0]

    Regards,

    Vijay

  • 0 in reply to Vijayendra Varma Siddamsetty
    Prodigy 59 points

    Hi Vijay,

    Thank you for providing the data format. Unfortunately, another problem was explored - for my case, lanerate = 4.9152 Gbps, a reference clock of 61.44 MHz is required. However, it is not possible to set this value: 

    When I set setupParams.fpgaRefClk = 61.44#184.32#, I receive the following error message:

    # File "C:\Users\TSV\Documents\Texas Instruments\Afe79xxLatte\lib\\AFE79xxLibraries\\AFE79xxLibraryPG1p0\\resourceFiles\mFuncDecorator.py", line 88, in inDecorator
# a=func(*args,**kwargs)
# File "C:\Users\TSV\Documents\Texas Instruments\Afe79xxLatte\lib\\AFE79xxLibraries\\AFE79xxLibraryPG1p0\\resourceFiles\mLmk.py", line 58, in lmkConfig
# self.lmkPllConfig(deviceRefClk,sysrefFreq,False)
# File "C:\Users\TSV\Documents\Texas Instruments\Afe79xxLatte\lib\\AFE79xxLibraries\\AFE79xxLibraryPG1p0\\resourceFiles\mFuncDecorator.py", line 88, in inDecorator
# a=func(*args,**kwargs)
# File "C:\Users\TSV\Documents\Texas Instruments\Afe79xxLatte\lib\\AFE79xxLibraries\\AFE79xxLibraryPG1p0\\resourceFiles\mLmk.py", line 249, in lmkPllConfig
# lmk.head.page.DCLK0_SDCLK1_controls.Out_control.dclkout_DIV_lt_4_0_gt_ = int(round(divInputClk/setupParams.fpgaRefClk)) #LMK04828 VCO = 2949.12MHz. FPGACLK = LMK04828VCO/12 = 245.76MHz.
# File "core\mEntity.py", line 159, in __setattr__
# File "core\mDataTypes.py", line 441, in setValue
# File "core\mDataTypes.py", line 479, in writeValue
# File "C:\Users\TSV\Documents\Texas Instruments\Afe79xxLatte\lib\\AFE79xxLibraries\\AFE79xxLibraryPG1p0\\resourceFiles\mlmkDevice.py", line 16, in writeProperty
# regVal = (regVal & r.zeros()) | (r.shift(value) & r.ones())
# File "core\reggie\mProperty.py", line 23, in shift
# TypeError: unsupported operand type(s) for 
# 
#

  • 0 in reply to Tomas Svoboda
    TI__Mastermind 18001 points

    Hi Tomas,

    This is an issue caused by the LMK. When using the LMKs PLL the VCO is 2949.12MHz and the LMK is not able to divide down to 61.44MHz, as the biggest divider value is '32'. To fix this issue you would need to provide an external clock to the LMK that will be used generate the AFE reference clock and the FPGA clocks. 

    I would suggest providing a 491.52MHz clock to the LMK_CLK_IN on the AFE EVM and setting changing the below settings in your script. 

    lmkParams.pllEn			= False
lmkParams.inputClk		= 491.52 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk	= True
setupParams.fpgaRefClk	= 61.44 # Should be equal to LaneRate/40 for TSW14J56

    Regards,

    David Chaparro