Part Number: AFE7950EVM
Other Parts Discussed in Thread: AFE7950
Hi Team,
I wanted to know if there is a way (non-GUI one) to estimate the power consumption of the AFE7950 chip coming with the AFE7950EVM for a particular AFE configuration.
What I consider currently is that only 1 ADC is receiving data (the rest are disabled with sysParams.rxEnable = [0, 0, 1, 1] - here ADC C and D are both still enabled but I am not sure if I can just disable C while leaving D enabled, and sysParams.fbEnable = [0, 0]), while all 4 DACs are transmitting data. FPGA is present in the system and is sending data to DACs, while receiving data from the ADC.
External clock reference is used, and is set to 122.76 MHz (12x10.23 MHz), ADC sampling rate is 2946.24 MHz, and DAC sampling rate is 11784.96 MHz. All ADC/DACs are single band and have the same data-rate 491.04 MHz.
ADC NCO is set to 1.5 GHz, and DAC NCOs are set to 3.2 GHz, 5.41 GHz, 8.3 GHz, and 9.8 GHz.
sysParams.jesdSystemMode = [3, 3].
Kind regards,
Željko
