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DAC38RF82: Some DAC AB channels have only NCO frequency output

Part Number: DAC38RF82
Other Parts Discussed in Thread: LMK00304, LMX2595

Hi team,

The customer have access to the DAC registers. The DAC is configured in 82121 mode. The line rate is 6.25 Gbps and the DAC sample clock is generated at 7.5 GSPS.

F = 1, k = 20, so Sysref generates 1.5625 MHz. The DAC device clock for the FPGA is 156.25 MHz. The DAC configuration is as follows: 

090000,
005823,
013080,
090004
311000,
3B2802,
3C8229,

090002,
0A8310,
0D0000,
190001,
240030,
256300,
4AFF03,
4B1300,
4C1307,
4D0101,
4E0F4F,
4F1C60,
51001F,
530000,
541CE7,

090001,
0A8310,
0D0000,
190001,
240030,
256300,
4AFF03,
4B1300,
4C1307,
4D0101,
4E0F4F,
4F1C60,
51001F,
530000,
541CE7,

090002,
240000,
5C0000,
090001,
240000,
5C0000,

090004,
0AFC03,
0A7C03,
090000,
005823,

090002,
240010,
5C0003,
090001,
240010,
5C0003,
090000,
005820,
090000,
040000,
050000,

850000,
850000,
850000,
850000,
850000,
850000,
850000,
850000,

090002,
278184,
0C2622,
1E5555,
1F5555,
201555,
1C0000,
280002,
280000,

090001,
278184,
0C2622,
1E5555,
1F5555,
201555,
1C0000,
280002,
280000,

Using the above configuration, in some DACs, the AB channel output is good and there is a transmitted single tone. But some of the DACs output only a 625-m NCO frequency. 

Could you help check this case? Thanks.

Best Regards,

Cherry

  • Cherry,

    When this issue occurs, what is the status of the SYNC signal?

    Are any errors reported in the following registers:

    Page 0, addresses 0x04 and 0x05

    Pages 1 and 2, addresses 0x41, 0x64-0x6B

    Regards,

    Jim 

  • Hi Jim,

    Thank you for the support.

    When this issue occurs, what is the status of the SYNC signal?

    The sync signal is pulled high, although occasionally pulled low, and then recovered. 

    Are any errors reported in the following registers:

    Page 0, addresses 0x04 and 0x05

    Pages 1 and 2, addresses 0x41, 0x64-0x6B

    Page 0, addresses 0x04 read back data is 0x0000 and 0x05 read back data is 0x0029.

    Pages 1, 0x41 registers read back as 0x0000 and 0x64-0x6B read back as 0x000A.

    Pages 2 is the same as pages 1. 

    Thanks and regards,

    Cherry

  • Cherry,

    This may be an issue with the SYSREF signal. Can they send their schematic for us to review? Is SYREF pulsed or continuous running?

    In the register writes above, I do not see a write to address 0x5C in page 1. This should be set to 0x03.

    Regards,

    Jim

  • Hi Jim,

    The original issue has been resolved.

    And here's a new case, JESD_SYSR_mode uses the 0x03 mode, after the jesd204b synchronization is complete, the DAC output is all normal, after which, the customer turns off the sysref signal to the DAC, and the jesd204b sync is normal, the sync signal is high, but the DAC has no output.

    All daughter cards use the same operating mode, but only one of the daughter cards outputs no signal after turning off the sysref signal. What might be the possible cause?

    Thanks and regards,

    Cherry

  • If they turn SYSREF back on, does DAC produce a valid output?

  • Hi Jim,

    If they turn SYSREF back on, does DAC produce a valid output?

    No, it still has no output.

    Regards,

    Cherry

  • Can they send a schematic showing how SYSREF is connected between the DAC and SYSREF source? Are they using a LMK device? Is SYSREF and device clock routed the same length on this DAC? What is the voltage swing and common mode voltage level of SYSREF?

  • Hi Jim,

    Can they send a schematic showing how SYSREF is connected between the DAC and SYSREF source?

    The RFoutB of the LMX2595 yields a SYSREF of 1.5625 MHz, which is given to the LMK00304 and outputs four SYSREF of the same source to four DAC chips. 

    Are they using a LMK device?

    LMX2595 and LMK00304 are being used.

    Is SYSREF and device clock routed the same length on this DAC?

    No, sysref length is approximately 11600 mil (without passing through an FMC connector in the middle) and sampling clock length is approximately 12300 mil (without passing through an FMC connector in the middle) .

    What is the voltage swing and common mode voltage level of SYSREF?

    The voltage swing is 1VPP and the common mode voltage is 0.5V.

    Thanks and regards,

    Cherry

  • SYSREF and sampling clock need to be the same length for deterministic latency. Is the length difference between CLK and SYSREF different for the other three DAC's?

    On the failing DAC, can the try and run a NCO test using SYSREF as the NCO and mixer SYNC source to see if SYSREF is getting received properly? See attached for more info regarding this test and the SYSREF alignment test.

    5153.SYSREF_NCO.pptx2112.SYSREF_register_test.docx