Other Parts Discussed in Thread: AFE8000
Hello, I am testing the TI-JESD204 IP for interfacing the AFE8000EVM.
My evaluation board is zcu102 and I connect afe8000evm to the HPC1 of zcu102. I am trying to use 64b/66b in the mode of subclass 1.
I didn't almost change the reference code for my zcu102.
Below are my change list.
In the file TI_204C_IP_ref.sv :
cfg_rx_scrambling_enabled : 1 --> 0
cfg_tx_scrambling_enabled : 1 --> 0
jesd_link_params.vh :
`define LANE_ADC_TO_GT_MAP {3'd5,3'd4,3'd6,3'd7,3'd3,3'd0,3'd2,3'd1}
`define LANE_DAC_TO_GT_MAP {3'd4,3'd5,3'd6,3'd7,3'd3,3'd0,3'd2,3'd1}
In the constraint file :
FPGA reference clock (refclk_p/n) is provided from G27 of zcu102 which is not modified.
sysref pins have been changed from AF11 to AH1 because AFE8000EVM has no connection to the original pins.
Pins for sys_clk_p/n also have changed from P10 to AE5.
Above lists were my change list.
I confirmed that the lane rate is 10.3125GHz and fpga reference frequency is 156.25MHz. Also, checked that the LMFS is 8821.
With the above and other parameters, I configured the all the settings for the AFE8000EVM as the attached excel file.
As you might notice it, I supply the reference clock for the LMK from the external signal generator. The frequency is 937.5MHz.
My bringup procedures are below.
1.First load browse the excel file.
2. Push the load Params button.
3. Push the Device Bringup button.
4. After pll locked message appeared in the latte log, load bit stream image to the zcu102.
5. In the hw_vios of Vivado, reset the master_reset_n.
6. After asserting master_reset_n, deassert the signal. Then, qpll0_locked changes to 0 to 3.
7. After that I reset the tx_sync_reset_vio, rx_sync_reset_vio.
8. In the TX side, sinusoidal signal is shown but in the Rx side, I can't see any signal nor rx_lane_data_valid is asserted.
Can you give any suggestion after checking this thread?
Below messages are shown in Latte log window
AFE80xxCatLibrary
spi - USB Instrument created.
resetDevice
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
Power Card - USB Instrument created.
Reset the FPGA and try again.
Loaded Libraries
FPGA Reset device not found
Reset the FPGA and try again.
FPGA Reset device not found
Loaded Configuration: AFE8000_SampleConfig.xlsx
Refreshed the GUI.
#================ ERRORS:4, WARNINGS:0 ================#
Loaded Configuration: AFE8000EVM_TI_JESD204C.xlsx
For these rates, 1KHz raster mode is not supported. Changing to 32-bit NCO mode.
In L=8 single link mode, the Sync Mux should be same for all mappers. Forcing the rxJesdTxSyncMux value to [0, 0, 0, 0]
Refreshed the GUI.
Device Initialization for ChipVersion: 2.0
The External Sysref Frequency should be an integer factor of: 1.627604MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 10312.5
laneRateRx1: 10312.5
laneRateFb: 10312.5
laneRateTx0: 10312.5
laneRateTx1: 10312.5
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 10312.5
laneRateRx1: 10312.5
laneRateFb: 10312.5
laneRateTx0: 10312.5
laneRateTx1: 10312.5
LMK Clock Divider - Device registers reset.
LMK Clock Divider - Device registers reset.
LMK and FPGA Configured.
DONOT_OPEN_Afe80xx_FULL - Device registers reset.
chipType: 0xa
chipId: 0x8001
chipVersion: 0x20
FPGA Reset device not found
FPGA Reset device not found
LMK and FPGA Configured.
AFE Reset Done
Fuse farm load autoload done successful
No autload error
Fuse farm load autoload done successful
No autload error
//Firmware Version = 9108
//PG Version = 1
//Release Date [dd/mm/yy] = 28/8/20
//Patch Version = 0
//PG Version = 0
//Release Date [dd/mm/yy] = 0/0/0
AFE MCU Wake up done and patch loaded.
PLL Locked
AFE PLL Configured.
AFE SerDes Configured.
AFE Digital Chains configured.
AFE TX Analog configured.
AFE RX Analog configured.
AFE FB Analog configured.
AFE JESD configured.
AFE AGC configured.
AFE PAP and Alarms configured.
AFE GPIO configured.
Sysref Read as expected
Setting RBD to: 11
Setting RBD to: 11
FPGA Reset device not found
FPGA Reset device not found
Setting RBD to: 11
###########Device DAC JESD-RX 0 Link Status###########
CS State TX0: 0b01010101 . It is expected to be 0b10101010
BUF State TX0: 0b00000000 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 0
###################################
###########Device DAC JESD-RX 1 Link Status###########
CS State TX0: 0b01010101 . It is expected to be 0b10101010
BUF State TX0: 0b00000000 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 1
###################################
AFE Configuration Complete
#================ ERRORS:6, WARNINGS:0 ================#
