AFE7950: Connecting DAC to ADC on the same board, using HSDC Pro and Latte

Hi David,

Once you configure the DAC tab of HSDC Pro and press 'Send' the FPGA will continuously send the tone you created. You can then loopback the DAC output to the ADC input and capture the tone you are sending in HSDC Pro. 

I recommend following the AFE+TSW14J57 bringup guide given in the AFE79xx secure folder, User's Guides and Software section, and then connecting the DAC outputs to the ADC input. 

Regards,

David Chaparro 

Thank you I'll try this. I was following the AFE7950 guide that talks about the TSWJ1456. I didn't realize there was a guide for the 57. 

I think the DAC output is working. I get the D3 "PLL 2 Locked" LED to light. Although in the guide it says i should get this to light as soon as I hit "send" but I always get an error first that the EVM to FPGA clock needs to be changed. I hit ok, hit send again, and nothing happens. However, the next page then says to run the S1 script. I do that, get 18 errors related to JESD sync, run the given "AFE.adcDacSync()" command in Latte, then hit Send again in HSDC Pro, and *then* I get the D3 LED to light on the EVM. So it seems the guide has the order of operations wrong?

However, in the ADC section, all I'm supposed to do is pick the ADC ini preset from the ADC list ("AFE79xx_2x2RX_24410" -- which i assume is correct although the TX preset for the DAC output is "AFE79xx_2x2TX_44210", not _24410 even though that's an option, but I don't know what the 2x2 or 5 digit numbers mean) -- and set the ADC output data rate to "245.76M". But when I hit the capture button, again, I get the message about the FPGA clock needing to be changed, and i hit capture again, and I can see it attempting to download the contents of RAM ("reading DDR" I think) but then I get a timeout error. No matter what I do, I always get hung up on this timeout error.

One other thing to note is that after getting the DAC to work (again, D3 and *only* D3 lights up) it says that D2 (TX sync) on the TSW14J57 board should be blinking, but what I actually see is D2 flashes *once* and only right when I hit send in the DAC screen. Just that one quick flash and then it stays off.

Hi David,

One thing to check is that the AFE is receiving 5V and the TSW 12V. Both power supplies should be capable of supplying 5A.

The sequence given in the PPT is correct and the FPGA should be configured to send data on the SERDES lanes before bringing up the AFE. Sometimes we see that the FPGA is not sending data and that we have to press the 'Send' button again and run the AFE.adcDacSync command. On your setup do you get any errors after pressing 'Send' again and running AFE.adcDacSync? 

The naming of the ini files "AFE79xx_2x2Rx_24410" corresponds to the AFE configuration. One thing to note is that the AFE is configured as two sub-chips, so most of the parameters will be given per sub-chip. The '2x2Rx' corresponds to the number of channels enabled, in this case all 2 channels in both subchips are enabled 4Rx. The 5 digit number at the end corresponds to the LMFS, JESD configuration, that the AFE is configured for and this should match the setting in the AFE script. 

To make sure the issue is not with the ini files you can copy the two files below to the following folders and restart HSDC Pro.

DAC ini file, AFE79xx_2x2TX_44210, should go to: C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J57revE Details\DAC files

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/220/AFE79xx_5F00_2x2TX_5F00_44210.ini

ADC ini file, AFE79xx_2x2RX_24410, should go to: C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J57revE Details\ADC files

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/220/AFE79xx_5F00_2x2RX_5F00_24410.ini

Regards,

David Chaparro

Thanks I'll try again. I just looked and I'm using the 12V supply that came with the TSW board, and I'm using my own 5V supply for the AFE board, but it's only rated for 3A. I'm noticing the connector is pretty hot. I figured the 5A requirement was just peak/surge/inrush and any bulk capacitance on that supply rail would take care of any current spikes. I'm guessing this 5V rail is connected to various SMPS'. Have you seen cases where excessive current that causes drooping on the 5V line affects performance or functionality? The only thing I have that goes that high is an ATX computer supply so I guess I'll have to use that.

You said that 2x2RX means "all 2 channels in both subchips" but the AFE7950 datasheet says it has 4 TX and 6 RX. I'm guessing those include FB channels. Just to be clear, I'm using a SMA-connector coax cable to connect from TXA to RXA, so one transmit and one receive. Is it a problem if I'm using the the guide that calls for the 2x2TX and 2x2RX ini setups but only connecting one transmit to one receive for this "loopback" testing I'm trying to do?

Ok I tried replacing the ini files, I'm using a supply with much higher current for each of the 12V and 5V power lines.

After hitting send the first time:

i get a popup that says "current lane rate is 9.8304G. JESD ref clk from EVM to TSWJ1457 needs to be 245.76M"

Hit ok, hit send again, no popup. D3 is ON on TSW, D3 is OFF on AFE (guide says EVM D3 should be on)

Immediately after running S1 script, AFE EVM D3 turns ON for a time, then OFF

During S1 execution, after D3 on AFE turns off, error in Latte log, “SPIA has not got control of PLL pages” followed by many messages “Waiting for MACRO_READY bit to go high” along with a count; which then changes to “[…] failed”. This all repeats again, SPIA error, MACRO_READY waiting, then fail. Eventually a count of “waiting for MACRO_DONE bit to go high” appears.

The S1 script takes about 10 minutes to complete. At the end it reports 59 errors. So I hit send again in HSDC Pro and run "AFE.adcDacSync()" and that produces the following result: 

###########Device DAC JESD-RX 0 Link Status###########

Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.

Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.

Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.

Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good.

CS State TX0: 0b00000000 . It is expected to be 0b10101010

FS State TX0: 0b00000000 . It is expected to be 0b01010101

Couldn't get the link up for device RX: 0; Alarms: 0x0

###################################

###########Device DAC JESD-RX 1 Link Status###########

Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.

Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.

Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.

Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good.

CS State TX0: 0b00000000 . It is expected to be 0b10101010

FS State TX0: 0b00000000 . It is expected to be 0b01010101

Couldn't get the link up for device RX: 1; Alarms: 0x0

###################################

#======

Again this whole time I've had TXA connected to RXA, but I've tried all this without doing that as well.  I haven't tried the ADC again.

One other thing of note: I tried running the S1 script again after reloading the ini file, and instead of waiting for it to finish, I just ran the adcdacsync command again, and it generated the same errors, but all of the power good LEDs on the AFE EVM went out. I'm using a very high current supply (ATX, 14A on the 5V rail, 12V can do 18A). Maybe the something reset? 

Regardless, I'm just getting nothing but weird behavior and nothing is working like the guide says.

Hi David,

Based on the fact that you are seeing LED D3, LMK PLL2 Locked, turn off during the bringup tells me that there may be an issue with the power. Once you run the S1 script the LMK should be programed and PLL2 should stay locked. It is possible that during the bringup the 3.3V rail is drooping causing the LMK to reset. During the AFE bringup do you see the current go up and then suddenly drop? 

Also, if you have long power cable you may need to bump up the 5V to the board, I use 5.6V, in order to account for the loss in the cable. 

For the "2x2Rx" ini file this is only referring to the Rx channels. The Fb channels have their own ini files that will be named "2x1FB". For looping back the DAC to one of the Rx channels you can continue to use the '2x2Rx' ini filed called out in the guide. 

Regards,

David Chaparro

Ok I'll check all voltages. Also, does it matter that I'm only connecting the one DAC output (TXA) to the one ADC input (RXA), with all other TX, RX, and FB sma connectors left open, not connected to anything? I did try connecting all TX to all RX, but that didn't help.

To be clear, the AFE EVM D3 only turns on during the start of the S1 script. I don't see it turn on after hitting Send in HSDC Pro.  And does it matter that I initially get that message in HSDC telling me I need to change the EVM to TSW clock to 245.76M? I see that instead of the D3 light coming on.

And for what it's worth, the AFE EVM does have all Power Good LEDs lit. I only ever saw those go out one time. They consistently come on and stay on after I apply power. Isn't that indication enough that my input power is good, since all downstream supplies are operating correctly?

Hi David,

For configuring the part it does not matter how the outputs/inputs are connected. The D3 on the AFE EVM should turn on and stay on after running the S1 script. It is a mistake in the guide that says it should turn on after pressing 'Send' in HSDC Pro. 

The initial message in HDSC Pro about the clock needing to be 245.76MHz is expected and it just a pop up letting you know what your SERDES rate is and the clock needed by the FPGA. The AFE script is already configured to match the SERDES rate and provide the 245.76MHz clock. 

You mentioned in your previous post that the D3, PLL2_LOCKED, LED turned off during the bringup. This indicates that there is an issue with the LMK and most likely it would be the power to the LMK. If the LED is not on then the AFE and FPGA will not be receiving the clocks that are required for bringup. 

Regards,

David Chaparro

Ok thanks for the reply. I am getting all PG indications. That said, my power supply is giving a bit lower than 5V at the test point. Again, I'm not sure if this matters since the downstream voltages are lower ( I would assume if the highest voltage on the board is 3.3V then the input needs to be something just above that to achieve regulation, plus I do have the power good on all supplies).

Just as a sanity check, I'm using the same 5V supply on another DAC board (DAC39J84EVM) and everything seems to work on that one (though the reason I'm using the AFE is because the ADC input on that is the only way to verify whether I'm getting a good output on its DAC since I don't have a spectrum analyzer or high speed scope; so even though the DAC board seems to be working, I can't actually measure its output to see if it's actually running).

Also, I would think if the LMK isn't working, or there is some power issue with it, then I'd *never* get a PLL2 lock, right? What I'm seeing is the D3 LED turn on for some amount of time after the S1 script begins, but then go out while the script is still running, and then doesn't come back on again.

Hi David,

To rule out the issue being the LMK we can program only the LMK and see if the PLL2 locked LED stays on. To program only the LMK you can run the script below. If the LED stays on after this running this script then this would point to a power issue that occurs when the AFE is being programmed. 

##############		Read me			##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 491.52M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_24410; Data Rate = 245.76M ---> To capture 4 RX channels
#In HSDC Pro ADC tab, Select AFE79xx_1x2FB_44210; Data Rate = 491.52M ---> To capture 2 FB channels

sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion

setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro 

##############		Top Level			##############
sysParams.FRef			= 491.52
sysParams.FadcRx		= 2949.12
sysParams.FadcFb		= 2949.12
sysParams.Fdac			= 2949.12*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
													
##############		Digital Chain		##############

		#####	RX	#####
sysParams.ddcFactorRx	=	[12,12,12,12]			#DDC decimation factor for RX A, B, C and D
sysParams.rxNco0		= 	[[9500,9500],			#Band0, Band1 for RXA 
							[9500,9500],        	#Band0, Band1 for RXB 
							[9500,9500],        	#Band0, Band1 for RXC 
							[9500,9500]]        	#Band0, Band1 for RXD 

		#####	FB	#####
sysParams.ddcFactorFb	=	[6,6]					#DDC decimation factor for FB 1 and 2
sysParams.fbNco0		= 	[9500,9500]				#Band0 for FB1 and FB2 

		#####	TX	#####
sysParams.ducFactorTx	=	[24,24,24,24]			#DUC interpolation factor for TX A, B, C and D
sysParams.txNco0		= 	[[9500,9500],			#Band0, Band1 for TXA 
							[9500,9500],        	#Band0, Band1 for TXB 
							[9500,9500],        	#Band0, Band1 for TXC 
							[9500,9500]]        	#Band0, Band1 for TXD


##############		JESD		##############

		#####	ADC-JESD	#####
sysParams.jesdSystemMode= [1,1]
													#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb -fb
													#SystemMode 1:	1R1F-FDD						; rx -rx -fb -fb
													#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
													#SystemMode 3:	1R								; rx -rx -rx -rx
													#SystemMode 4:	1F								; fb -fb- fb -fb
													#SystemMode 5:	1R1F-TDD						; rx/fb-rx/fb-rx/fb-rx/fb
													
sysParams.jesdTxProtocol= [0,0]						# 0 - 8b/10b encoding; 2 - 64b/66b encoding 
sysParams.LMFSHdRx		= ["24410","24410","24410","24410"]
													# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
													# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb		= ["22210","22210"]

sysParams.rxJesdTxScr	= [True,True,True,True]
sysParams.fbJesdTxScr	= [True,True]

sysParams.rxJesdTxK		= [16,16,16,16]
sysParams.fbJesdTxK		= [16,16]

sysParams.jesdTxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location. 
													# For example, if you want to exchange the first two lines of each 2T,
													#		this should be [[1,0,2,3],[5,4,6,7]]

		#####	DAC-JESD	#####
sysParams.jesdRxProtocol= [0,0]
sysParams.LMFSHdTx		= ["44210","44210","44210","44210"]
sysParams.jesdRxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location.
													# For example, if you want to exchange the first two lines of each 2R
													#		this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd		= [4, 4]
sysParams.jesdRxScr		= [True,True,True,True]
sysParams.jesdRxK		= [16,16,16,16]

		#####	JESD Common	#####
	
sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack	= 1	#JESD Sync signal is connected to FPGA

##############		GPIO		##############
sysParams.gpioMapping	= {
						'H8': 'ADC_SYNC0',
						'H7': 'ADC_SYNC1',
						'N8': 'ADC_SYNC2',
						'N7': 'ADC_SYNC3',
						'H9': 'DAC_SYNC0',
						'G9': 'DAC_SYNC1',
						'N9': 'DAC_SYNC2',
						'P9': 'DAC_SYNC3',
						'P14': 'GLOBAL_PDN',
						'K14': 'FBABTDD',
						'R6': 'FBCDTDD',
						'H15': ['TXATDD','TXBTDD'],
						'V5': ['TXCTDD','TXDTDD'],
						'E7': ['RXATDD','RXBTDD'],
						'R15': ['RXCTDD','RXDTDD']}

##############		LMK Params		##############
lmkParams.pllEn			= True
lmkParams.inputClk		= 983.04 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk	= True
setupParams.fpgaRefClk	= 245.76 # Should be equal to LaneRate/40 for TSW14J56

##############		Logging		##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x0 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1

device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
setupParams.skipLmk = False
AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode = False
AFE.LMK.lmkConfig()

Also, I would still suggest increasing the power supply voltage to 5.5V and see if this helps at all. 

Regards,

David Chaparro 

Thanks I'll try that.

Unfortunately I don't have a programmable/vaariable power supply. I'm using an ATX (i.e., desktop computer) power supply because it's all I have that can deliver the required current. If the script you gave works, I'll look into figuring out how to get a supply that I can set the voltage on that also has high enough current.

ok I ran the following: setup.py, devInit.py, then the script you sent. After that, D3 comes on and stays on. I'm guessing the high power draw occurs during AFE programming, and this must cause a sag on the 5V input. I put a scope on it while running S1, and sure enough it drops significantly, below 4V it seems.

I guess that means the LMK or another device is probably losing 3.3V (although I don't see the power good LED go out) and/or going into brownout reset.

I'll work on getting another supply.

ok i think my 5V supply is good now. It's still reading a little low at the connector, but now the D3 PLL 2 LOCKED stays on.

However, when I hit send in HSDC Pro, instead of the TSW D2 (TX CLK) blinking continuously, it just flashes once right after I hit send, and then stays off. I tried the AFE.adcDacSync() command and it's similar (though a bit better?) as when I ran it before:

###########Device DAC JESD-RX 0 Link Status###########

CS State TX0: 0b10101010 . It is expected to be 0b10101010

FS State TX0: 0b00000000 . It is expected to be 0b01010101

Couldn't get the link up for device RX: 0; Alarms: 0x0

###################################

###########Device DAC JESD-RX 1 Link Status###########

CS State TX0: 0b10101010 . It is expected to be 0b10101010

FS State TX0: 0b00000000 . It is expected to be 0b01010101

Couldn't get the link up for device RX: 1; Alarms: 0x0

###################################

#======

D3 on the TSW is lit (RX Sync), D1 is not lit (TX Sync), D2 is not lit (TX CLK), D4 is not lit (RX CLK), D7 is not lit (MEM SUCCESS).

On the AFE EVM, D1 (STAT 0), D2 (STAT 1), and D4 (LMK LOCKED) are all off. Only D3 (PLL 2 LOCKED) is lit.

Ok sorry for all the back and forth. I'm working on getting a programmable high current power supply, a function generator, and a ghz oscilloscope. once i have all that and try this out again, i can either report back here or start a new post if there are issues.