AFE7950: Problem reconfiguring the zcu102_64b66b FPGA reference design from a 8 lane design to a 2 lane design

Joseph Cullen

Part Number: AFE7950

I have run into a problem porting the zcu102_64b66b reference design from a 8 lane design to a 2 lane design. The TI xzcu102 64/66 bit reference design with 8 JESD lanes, for evaluation of the AFE7950 on the EVM7950 works reliably with 8 lanes as supplied but does not work when reconfigured to work over 2 lanes with the porting changes. The TX side, ie DAC side is delivering tones however the RX side never demonstrates a data valid active in the FPGA to indicate that the FPGA transceiver is locking on to a valid JESD stream from the AFE7950. The following is a capture of the behavior on the RX side as captured using the Vivado HW debug tool integrated with the design. I have also included a document detailing the changes that I determined as necessary from the instruction supplied with the reference design. I would appreciate any help with uncovering why this is not working. Thanks

Debug_2_Lane.docx

over 1 year ago

0 David Chaparro over 1 year ago

TI__Genius 17881 points

Hi Joseph,

In addition to the changes made in the jesd_link_params file there are three more changes that should be required.

These changes are described below:

1. Update the Transceiver wizard to select the lanes being used by the AFE and set the correct lane rate

2. Update the data packing, refdesign_tx. for the new LMFS

reg [3:0] sine_count;

always @(posedge tx_sys_clock or negedge master_reset_n)
begin
	if (!master_reset_n)
	 sine_count <= 4'd0;
	else
	 if (tx_lane_data_ready)
	  sine_count <= sine_count + 1;
end

assign tx_lane_data[0][63 -: 16] = sine_i[0][63 - sine_count*4];
assign tx_lane_data[0][47 -: 16] = sine_i[0][62 - sine_count*4];
assign tx_lane_data[0][31 -: 16] = sine_i[0][61 - sine_count*4];
assign tx_lane_data[0][15 -: 16] = sine_i[0][60 - sine_count*4];

assign tx_lane_data[1][63 -: 16] = sine_q[0][63 - sine_count*4];
assign tx_lane_data[1][47 -: 16] = sine_q[0][62 - sine_count*4];
assign tx_lane_data[1][31 -: 16] = sine_q[0][61 - sine_count*4];
assign tx_lane_data[1][15 -: 16] = sine_q[0][60 - sine_count*4];

assign tx_lane_data[2][63 -: 16] = sine_i[1][63 - sine_count*4];
assign tx_lane_data[2][47 -: 16] = sine_i[1][62 - sine_count*4];
assign tx_lane_data[2][31 -: 16] = sine_i[1][61 - sine_count*4];
assign tx_lane_data[2][15 -: 16] = sine_i[1][60 - sine_count*4];

assign tx_lane_data[3][63 -: 16] = sine_q[1][63 - sine_count*4];
assign tx_lane_data[3][47 -: 16] = sine_q[1][62 - sine_count*4];
assign tx_lane_data[3][31 -: 16] = sine_q[1][61 - sine_count*4];
assign tx_lane_data[3][15 -: 16] = sine_q[1][60 - sine_count*4];

3. Update the data unpacking, in refdesign_rx, for the new LMFS. The new unpacking is given below.

(*dont_touch = "true"*) wire [ADC_RES-1:0] ch1_I_sample;
(*dont_touch = "true"*) wire [ADC_RES-1:0] ch1_Q_sample;
(*dont_touch = "true"*) wire [ADC_RES-1:0] ch2_I_sample;
(*dont_touch = "true"*) wire [ADC_RES-1:0] ch2_Q_sample;
(*dont_touch = "true"*) wire [ADC_RES-1:0] ch3_I_sample;
(*dont_touch = "true"*) wire [ADC_RES-1:0] ch3_Q_sample;
(*dont_touch = "true"*) wire [ADC_RES-1:0] ch4_I_sample;
(*dont_touch = "true"*) wire [ADC_RES-1:0] ch4_Q_sample;

assign ch1_I_sample = rx_lane_data[0][63-16*0 -: ADC_RES];
assign ch1_Q_sample = rx_lane_data[0][63-16*1 -: ADC_RES];
assign ch2_I_sample = rx_lane_data[0][63-16*2 -: ADC_RES];
assign ch2_Q_sample = rx_lane_data[0][63-16*3 -: ADC_RES];

assign ch3_I_sample = rx_lane_data[1][63-16*0 -: ADC_RES];
assign ch3_Q_sample = rx_lane_data[1][63-16*1 -: ADC_RES];
assign ch4_I_sample = rx_lane_data[1][63-16*2 -: ADC_RES];
assign ch4_Q_sample = rx_lane_data[1][63-16*3 -: ADC_RES];

Regards,

David Chaparro

RF & microwave

RF & microwave forum

AFE7950: Problem reconfiguring the zcu102_64b66b FPGA reference design from a 8 lane design to a 2 lane design