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Original question:

AFE7769DEVM: Serdes TX and RX return loss data

AFE7769DEVM: AFE7769DEVM PCB loss data, dk and df

Alder Lim
Prodigy 190 points

Part Number: AFE7769DEVM

Hi TI team,

I am looking at the AFE7769DEVM and i am thinking to take it as a reference for my PCB design. What is the material for the AFE7769DEVM PCB? and what is the dk and df value for the PCB as well.

Thanks,
Best regards,
Alder

  • 0
    TI__Guru* 82905 points

    Hi Alder,

    It is FR4 based. We can follow-up with the stack-up information

    -Kang

  • 0
    TI__Expert 3546 points

    Hi Alder,

    Thank you for your question! The material involved is 370HR from Isola. The following link expands on the material specs:

    https://www.isola-group.com/wp-content/uploads/data-sheets/370hr-laminate-prepreg.pdf?t=256748982 

    Please let us know if you have further questions. Thank you!

    Best regards,

    Simran

  • 0 in reply to Simran Nanda
    Prodigy 190 points

    Thank Simran for the material info.

    370HR Df=0.021 which is high and it contribute quite a lot on the loss per length for the routing side.

    For JESD204B, the insertion loss is about 4dB, as picture shown below. 

    When consider with the routing length loss, FMC connector loss, seem we do not have much margin on the mating side, am i right?

  • 0 in reply to Alder Lim
    TI__Expert 3546 points

    Hi Alder,

    When it comes to JESD204B we have validated our FPGA and AFE7769DEVM's JESD connection with a SerDes rate of 9.8Gbps. What may help bring more clarity is if you could provide more information around your design:

    • Which FPGA are you using for your design, and do you have a board design/schematic?
    • What is the planned SerDes lane rate for the design?
    • What are the intended SerDes trace lengths on both the FPGA and board that is being designed based on the AFE7769DEVM? In addition, what layer do you plan to route the traces on?

    Thank you!

    Best regards,

    Simran

  • 0 in reply to Simran Nanda
    Prodigy 190 points

    Hello Simran,

    • Which FPGA are you using for your design, and do you have a board design/schematic?

    Intel Agilex 5

    • What is the planned SerDes lane rate for the design?

    Per JESD204B spec, 12.5Gbps and JESD204C, looking for upto 28Gbps

    • What are the intended SerDes trace lengths on both the FPGA and board that is being designed based on the AFE7769DEVM? In addition, what layer do you plan to route the traces on?

    4.5 inches, from FPGA to reach the FMC connector. Layer 7, L14 with M4 material.

    Thanks,
    Best regards,
    Alder

  • 0 in reply to Alder Lim
    TI__Expert 3546 points

    Hi Alder,

    Thank you for the information. For our designs where signal integrity is a top priority, we have built our hardware using the Panasonic Megtron 6 R-5775K and R-5670K. 

    Best regards,

    Simran

  • 0 in reply to Simran Nanda
    Prodigy 190 points

    Hi Simran,

    Panasonic Megtron 6 makes more sense in state of 370HR from Isola. 

    I have the evm .brd file and I have the PCB materials, I can calculate the lost now.

    Thanks,
    Best regards,
    Alder