AFE7950EVM: Block design of Vivado project - ZCU102_AFE79xx_64b66b_12Gbps.zip example

Vitor Cristina

Part Number: AFE7950EVM
Other Parts Discussed in Thread: AFE7950

Hello!

I am using de AFE7950 EVM with the Xilinx Zynq Ultrascale+ MPSoC ZCU102 Evaluation Kit. I found out on your secure software page (www.ti.com/.../autopagepreview.tsp some zip folders with some examples on how to integrate the AFE7950 with the ZCU102 (for exemple ZCU102_AFE79xx_64b66b_12Gbps.zip).

In this folder I only get access to the bit file generated by Vivado. I also have acces to the IPs that you use in this project, but is it possible to have access to the block design (.bd) ? I want to change the signal that we want to transmit. This signal is defined of FPGA code.

Thank you!

over 1 year ago

0 David Chaparro over 1 year ago

TI__Genius 17671 points

Hi Vitor,

The reference design that you are referencing does not use a block design and only incorporates the rtl code. All of these files are found in the zip file that you mention.

Regards,

David Chaparro

0 Vitor Cristina over 1 year ago in reply to David Chaparro

Prodigy 60 points

Hi David,

Can you please check my new question? https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1300626/afe7950evm-afe7950evm

I followed your documentation, imported all files that you sugest and I don´t get the the debug tabs that is supposed to.

0 David Chaparro over 1 year ago in reply to Vitor Cristina

TI__Genius 17671 points

Hi Vitor,

I have responded on your other e2e post.

Regards,

David Chaparro

RF & microwave

RF & microwave forum

AFE7950EVM: Block design of Vivado project - ZCU102_AFE79xx_64b66b_12Gbps.zip example