Other Parts Discussed in Thread: TSW14J57EVM, AFE7950, AFE7950EVM
Tool/software:
Hi
I am taking the first steps to master the AFE7950 using the TSW14J57EVM using the AFE7950+TSW14J57.pptx method.
At step 5, instead of one harmonic at a frequency of (9500+9.9525) MHz, I see two harmonics at frequencies 9505 and 9509 MHz. What causes the harmonic at 9505 MHz?
There are no problems with powering the devices: directly on the AFE7950EVM board 5.1 V (current 3.7 A), directly on the TSW14J57EVM board 12.1 V (current 1.8 A).
I am attaching explanatory screenshots and logLatte.
Thanks in advance, Andrey
#======
#Executing .. AFE7950/bringup/setup.py
#Start Time 2024-06-18 11:35:38.878000
AFE79xxLibraryPG1p0
spi - USB Instrument created.
resetDevice
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
#Done executing .. AFE7950/bringup/setup.py
#End Time 2024-06-18 11:35:48.111000
#Execution Time = 9.23300004005 s
#================ ERRORS:0, WARNINGS:0 ================#
#======
#Executing .. AFE7950/bringup/devInit.py
#Start Time 2024-06-18 11:39:22.260000
Power Card - USB Instrument created.
Reset the FPGA and try again.
Loaded Libraries
Refreshed GUI
#Done executing .. AFE7950/bringup/devInit.py
#End Time 2024-06-18 11:40:48.178000
#Execution Time = 85.9179999828 s
#================ ERRORS:1, WARNINGS:0 ================#
#======
#Executing .. AFE7950/bringup/S1_OnboardClk_RX_250M_TX_FB_500M.py
#Start Time 2024-06-18 11:45:28.578000
The External Sysref Frequency should be an integer factor of: 3.84MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 9830.4
laneRateFb: 9830.4
laneRateTx: 9830.4
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 9830.4
laneRateFb: 9830.4
laneRateTx: 9830.4
LMK Clock Divider - Device registers reset.
LMK Clock Divider - Device registers reset.
REFCLOCK is used from LMK source, ensure board connections are ok to do the same
LMK and FPGA Configured.
DONOT_OPEN_Atharv_FULL - Device registers reset.
chipType: 0xa
chipId: 0x78
chipVersion: 0x11
AFE Reset Done
Fuse farm load autoload done successful
No autload error
Fuse farm load autoload done successful
No autload error
AFE MCU Wake up done and patch loaded.
PLL Locked
AFE PLL Configured.
AFE SerDes Configured.
AFE Digital Chains configured.
AFE TX Analog configured.
AFE RX Analog configured.
AFE FB Analog configured.
AFE JESD configured.
AFE AGC configured.
AFE GPIO configured.
Sysref Read as expected
###########Device DAC JESD-RX 0 Link Status###########
Serdes-FIFO error for lane 0: 1
Serdes-FIFO error for lane 1: 1
Serdes-FIFO error for lane 2: 1
Serdes-FIFO error for lane 3: 1
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good.
CS State TX0: 0b00000000 . It is expected to be 0b10101010
FS State TX0: 0b00000000 . It is expected to be 0b01010101
Couldn't get the link up for device RX: 0; Alarms: 0xf000
###################################
###########Device DAC JESD-RX 1 Link Status###########
Serdes-FIFO error for lane 0: 1
Serdes-FIFO error for lane 1: 1
Serdes-FIFO error for lane 2: 1
Serdes-FIFO error for lane 3: 1
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good.
CS State TX0: 0b00000000 . It is expected to be 0b10101010
FS State TX0: 0b00000000 . It is expected to be 0b01010101
Couldn't get the link up for device RX: 1; Alarms: 0xf000
###################################
AFE Configuration Complete
#Done executing .. AFE7950/bringup/S1_OnboardClk_RX_250M_TX_FB_500M.py
#End Time 2024-06-18 11:46:08.822000
#Execution Time = 40.243999958 s
#================ ERRORS:18, WARNINGS:1 ================#
###########Device DAC JESD-RX 0 Link Status###########
CS State TX0: 0b10101010 . It is expected to be 0b10101010
FS State TX0: 0b01010101 . It is expected to be 0b01010101
Could get the link up for device RX: 0
###################################
###########Device DAC JESD-RX 1 Link Status###########
CS State TX0: 0b10101010 . It is expected to be 0b10101010
FS State TX0: 0b01010101 . It is expected to be 0b01010101
Could get the link up for device RX: 1
###################################
#======
###########Device DAC JESD-RX 0 Link Status###########
CS State TX0: 0b10101010 . It is expected to be 0b10101010
FS State TX0: 0b01010101 . It is expected to be 0b01010101
Could get the link up for device RX: 0
###################################
###########Device DAC JESD-RX 1 Link Status###########
CS State TX0: 0b10101010 . It is expected to be 0b10101010
FS State TX0: 0b01010101 . It is expected to be 0b01010101
Could get the link up for device RX: 1
###################################
#======
###########Device DAC JESD-RX 0 Link Status###########
CS State TX0: 0b10101010 . It is expected to be 0b10101010
FS State TX0: 0b01010101 . It is expected to be 0b01010101
Could get the link up for device RX: 0
###################################
###########Device DAC JESD-RX 1 Link Status###########
CS State TX0: 0b10101010 . It is expected to be 0b10101010
FS State TX0: 0b01010101 . It is expected to be 0b01010101
Could get the link up for device RX: 1
###################################
#======
###########Device DAC JESD-RX 0 Link Status###########
CS State TX0: 0b10101010 . It is expected to be 0b10101010
FS State TX0: 0b01010101 . It is expected to be 0b01010101
Could get the link up for device RX: 0
###################################
###########Device DAC JESD-RX 1 Link Status###########
CS State TX0: 0b10101010 . It is expected to be 0b10101010
FS State TX0: 0b01010101 . It is expected to be 0b01010101
Could get the link up for device RX: 1
###################################
#======
###########Device DAC JESD-RX 0 Link Status###########
CS State TX0: 0b10101010 . It is expected to be 0b10101010
FS State TX0: 0b01010101 . It is expected to be 0b01010101
Could get the link up for device RX: 0
###################################
###########Device DAC JESD-RX 1 Link Status###########
CS State TX0: 0b10101010 . It is expected to be 0b10101010
FS State TX0: 0b01010101 . It is expected to be 0b01010101
Could get the link up for device RX: 1
###################################
#======