AFE8030EVM: Observing MHz Frequency offset

Shiva,

We can take a look at your configuration. However, you will need to measure the AFE clock firstly to ensure there are no frequency offset amongst the AFEs. The AFE NCOs are digitally controlled with > 32bit of frequency accuracy. If the frequency is off, then most likely the AFE clock itself is wrong. Please check this firstly to ensure all AFE clocks are consistent.

-Kang

Hi Kang ,

As we are taking clock and sysref from LMK0428 on board for AFE8030 and to our FPGA.

Can you suggest any test point to verify the LMK clock on AFE EVK

Regards

P Shiva

Shiva,

Can you please probe the DCLKOUT2 output of the LMK (net CLK_p and CLK_N) and confirm their frequency?

Can you share why you are using DAC IQ mode? Could you try changing to DAC non-interleaving mode and report if that has any impact?

Regards,

Ben

Hi Ben,

I have changed the config to DAC non-interleaving mode but there is no effect.

we have probed R326 (DCLKOUT2) we observed clock error as we configured for 245.76Mhz but we see 247.63Mhz i think this is the issue for ~35Mhz at 4.4Ghz. i am attaching the Hex register values which we are using to program LMK04828. suggest how to resolve this issue ?  

Regards

P Shiva

unsigned int LMK_arr[136] = {0x000090,0x000010,0x000200,0x000306,0x0004D0,0x00055B,0x000600,0x000C51,0x000D04,0x01000C,0x010155,0x010255,0x010301,0x010420,0x010500,0x010670,0x010711,0x01080C,0x010955,0x010A55,0x010B01,0x010C20,0x010D00,0x010E70,0x010F11,0x011008,0x011155,0x011255,0x011300,0x011402,0x011500,0x0116F9,0x011700,0x011818,0x011955,0x011A55,0x011B00,0x011C02,0x011D00,0x011EF9,0x011F33,0x012008,0x012155,0x012255,0x012300,0x012402,0x012500,0x0126F1,0x012700,0x012808,0x012955,0x012A55,0x012B00,0x012C02,0x012D00,0x012EF9,0x012F00,0x01300C,0x013155,0x013255,0x013301,0x013420,0x013500,0x013671,0x013701,0x013820,0x013903,0x013A09,0x013B00,0x013C00,0x013D00,0x013E03,0x013F00,0x014001,0x014100,0x014200,0x014311,0x0144FF,0x01457F,0x014610,0x01471A,0x014833,0x014942,0x014A33,0x014B16,0x014C00,0x014D00,0x014EC0,0x014F7F,0x015003,0x015102,0x015200,0x015300,0x015478,0x015500,0x01567D,0x015700,0x015896,0x015906,0x015A00,0x015BD4,0x015C20,0x015D00,0x015E00,0x015F0B,0x016000,0x016101,0x016244,0x016300,0x016400,0x01650C,0x0171AA,0x017202,0x017C15,0x017D33,0x016600,0x016700,0x01680C,0x016959,0x016A20,0x016B00,0x016C00,0x016D00,0x016E13,0x017300,0x018200,0x018300,0x018400,0x018500,0x018800,0x018900,0x018A00,0x018B00,0x1FFD01,0x1FFE01,0x1FFF01};

Hi Shiva,

Please check your crystal oscillator input (122.88MHz) and check potentially any soldering issues. The LMK04828 setting, if you have copied from the Latte GUI, had been tested thoroughly. This is most likely a hardware issue.

-Kang

Hi Kang,

As we have done some Rework to enable clock and SPI access PFA of Rework .can you please suggest the  Resistors to check to find the Hardware issue .TI board Rework.pdf

Regards

P Shiva

Shiva,

Do you have the TICSpro .tcs file for programming the LMK04828?  If not can you confirm if your configuration is different than the latte GUI?  

Regards,

Will

Hi william

PFA tcs file

exp_jun26.tcs

Regards

P Shiva

Shiva,

I will get back to you tomorrow.

Regards,

Will

Shiva,

I loaded your .tcs file onto our EVM and do not notice any problems.  The lock time for PLL1 takes a few seconds, but other than that it looks good.  I tested DCLKOut2 and was not seeing any stability problems at 245.76MHz.  Could you give more detail to your specific problem?

Regards,

Will

Hi Will,

we have total of 7 setups with Hitek +TI (AFE8030EVK) from which first setup is we received directly from TI and other 6 setups we got it from Sivers semiconductors .in these setups  we are observred the at ~35Mhz frequency offset in 4.4Ghz AFE8030 configurations .so we tested the LMK output clock which we observed the 247.63Mhz. we are not sure what is the problem .we need to know why we are seeing this DCLKOut2 output as 247.63Mhz.we can have a meet if you detailed want to debug the AFE8030EVK

Regards

P Shiva

Shiva,

I understand.  What VCXO are you using with the LMK04828?

Regards,

Will

Hi will,

sorry for late reply .we are using 122.88 crystal as the VCXO for LMK04828

Regards

P Shiva

Shiva,

What model number VCXO?

Regards,

Will

Hi will ,

In working Setup the VCXO model number is CRYSTEK CVHD-950(2135-01) in the non-working setup CRYSTEK CVHD-950X(2227-02) . Will this be the problem ?

Regards

P Shiva

Shiva,

Just to confirm -

With the CRYSTEK CVHD-950(2135-01) you have a working setup.  But with the exact same programming and hardware setup the CRYSTEK CVHD-950X(2227-02) is not working?

I will confirm if this VCXO poses any risk.

Regards,

Will

Hi will,

yes with the same setup and different AFE8030 evk .one evk is having  CRYSTEK CVHD-950(2135-01) which is working but other evk is having CRYSTEK CVHD-950X(2227-02) which is not working(seeing the output of LMK as  247.63Mhz).

Regards

P Shiva

Shiva,

The VCXO should not be the problem.  The CVHD-950X is just a higher temperature variant and this should not change anything.

Shiva Pinagani said:

6 setups we got it from Sivers semiconductors

For the shivers setups that all are not working can you share the schematics of the board you are using? Or at least around the LMK04828?

Your output makes me think that the PLL is not locking.  Could you share if the Status_LD2is high? My guess is it is not.  From there can you measure the input control voltage to the VCXO on the failing boards? There may be a loop filter problem on these boards if they are all not locking.

The loop filter for PLL1 is defined as:

After this try disabling holdover and see what happens.  Holdover is enabled by setting R336 Bit 0 to 1.

Let me know if you have any questions.

Will