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Original question:

AFE8030EVM: Observing MHz Frequency offset

LMK04828 setup on AFE8030 EVM

vamsi bolla
Prodigy 10 points
Part Number: AFE8030EVM
Other Parts Discussed in Thread: LMK04828

Tool/software:

HI william pfennigwerth,

i am vamsi dealing with the offset issue in place of shiva, in the latest message you have mentioned about to check the PLL lock on the board,yes we have seen PLL is not locking(Status_LD2 is not high).in that you have mentioned that by disabling the R336 bit .for this problems  can you help me with these

1)can you tell me at which point need to check the voltage of VCXO

2) how to change the R336 bit

  • 0
    TI__Mastermind 21451 points

    Hello Vamsi, 
    1. You need to check the tuning voltage pin of the VCXO - aka vtune. 

    2. I don't follow your question here? 
    You need to program our device via SPI to change register settings. In this case Will asked you to disable holder by 0x150[0] to '0'. 

    Programming instructions are found on page 32 of DS. 

    Best regards, 

    Vicente 

  • 0 in reply to vicente flores prado
    Prodigy 10 points

    i have tried for the both enable and disable of the holdover bit but no pll lock and even vtune is seen 3.3v

  • 0 in reply to vamsi bolla
    TI__Mastermind 21451 points

    Can you share your most up to date configuration and schematic 

    do you have a lock tree or block diagram of your system by chance?

    Best regards,

    Vicente

  • 0 in reply to vicente flores prado
    Prodigy 10 points

    Actually when i restart board and programming, firstly pll is getting locked then after lmk is locking and seen that eye margin as 0.after when i update the RX- DSA,attentuaion and channel then  reprogrammed then only lmk is getting locked with proper eye margin where pll is not.

  • 0 in reply to vamsi bolla
    TI__Mastermind 21451 points

    Hi Vamsi, 
    Can you please elaborate I don't quite understand the issue here. 

    In both instances the LMK04828 is locked?
    Best regards, 

    Vicente 

  • 0 in reply to vicente flores prado
    Prodigy 10 points

    1)Actually when ever i used to program for 1st time after reboot we have seen that PLL led is high before LMK is high (i.e before LMK lock PLL is locking) at that time we have seen eye margin is 0. After  programming for 2nd time or more times,we have seen only LMK  is locking but PLL is not locking and I eye margin is proper.

    note:in both instances LMK is locking but

    in first instance,PLL is locking before LMK lock(it is happening for the 1st time after reboot from 2nd time only LMK is locki g but not PLL)

    in 2nd instance only LMK is locking but not PLL 

    below is the block Diagram
    for clarification find the image

    Scenario 1
    • Condition: LD_Status1 (LMK Locked LED is ON), LD_Status2 (PLL Locked LED is OFF)
    • Outcome: Eye margin is good
    Scenario 2
    • Condition: Both LD_Status1 (LMK Locked LED is ON) and LD_Status2 (PLL Locked LED is ON)
    • Outcome: Eye margin is zero
    NOTE: After LMK PLL has to be locked 
     
  • 0 in reply to vamsi bolla
    TI__Mastermind 21451 points

    Hello Vamsi, 
    In scenario one I believe you have you have not properly configured the device. 
    I find it interesting that you report good eye margin when our device is unlocked. This does not make any sense to me. 

    Can I receive entire schematic please? I believe you're using both PLL1 & PLL2 given you seem to be utilizing both status pins as lock detect. 

    Have you checked the clkouts in the unlocked cases? I wouldn't expect you to have an output or if you did - it wouldn't be stable. 
    Can you share a clock tree and the config file you're using? 
    Entire Schematic + clock tree + config will really help me determine what your requirements are and get an initial idea of what's actually wrong. 

    If you can't post, your schematic here you can create a new question on the internal thread which is not available to public, or you can email me: v-floresprado@ti.com 

    Best regards, 

    Vicente 

  • 0 in reply to vicente flores prado
    Prodigy 10 points

    Hi vicente, gentle reminder i have shared you the schematics and configs to v-floresprado@ti.com can you please check them and we have checked the clkout, as you said they are not stable,

  • 0 in reply to vamsi bolla
    TI__Mastermind 21451 points

    Hi Vamsi, 
    Closing this thread as we have taken this conversation offline. 

    Best regards, 

    Vicente