Tool/software:
Hello support team,
We have designed a custom AFE7900 board with identical front end chain for each individual ADC channels ( Channel A, Channel B, Channel C, Channel D). Each channel is having frequency range of 35-60 MHz. all channels are having identical transmission line lengths and lumped components.
I am capturing IQ digital data for each channels with ZCU102 FPGA board. from the captured digital IQ data, I have calculated the relative phase difference between channel A and B, Channel A and C, channel A and D, channel B and C.
from the calculations, I found out that the there is some fixed phase difference delay as below
When I am providing same identical RF inputs to channel A, channel B, Channel C, and Channel D with 0 deg phase difference from function generator. below is what I am getting from the captured IQ through calculations of inverse tan of (Q/I) and phase difference of channel A inverse tan of (Q/I) - Channel B inverse tan of (Q/I).
35 MHz = channel A - channel B = 2.3 deg
45 MHz = channel A - channel B = 5 deg
60 MHz = channel A - channel B = 7.7 deg
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35 MHz = channel A - channel C = 2.8 deg
45 MHz = channel A - channel C = 5.2 deg
60 MHz = channel A - channel C = 8 deg
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35 MHz = channel A - channel D = 2 deg
45 MHz = channel A - channel D = 3.8 deg
60 MHz = channel A - channel D = 5.5 deg
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35 MHz = channel B - channel C = 0.4 deg
45 MHz = channel B - channel C = 0.8 deg
60 MHz = channel B - channel C = 2 deg
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what could be the reason of this fixed phase difference variation when I am providing identical RF inputs with 0 deg phase difference? (as we have done proper length matching as well for the JESD serdes lines and all 4 input RF channels are identical in terms of transmission line length and components). and Is there any way inside AFE7900 to compensate for phase difference ?
Kindly request you to provide guidance for this. This is important for us as we are measuring relative phase from the captured IQ digital data.