Hello TI forum,
In the JESD204B/C frame assembly table (datasheet pg 170) for 4RX and 1 DDC per RX chain, at 375 MHz interface rate/output rate, at 16 bit resolution and 8/10b encoding, the frame assembly table lists 4-8-3-1-0 as a valid LMFS number which would give you a lane/serdes rate of 11.25Gbps.
However, when you do the math for what lane rate you need to support a 375 MHz interface rate based on the AFE79xx_Configuration_Parameters.pdf found in Guides_and_SW. For 4 lanes, 8 converters, 375 MHz interface rate with 8/10b encoding, you would need a lane rate of at least 15 Gbps.
The math for that looks like this:
Lane rate =
(sample rate/(decimation) x (bits/sample) x (encoding) x (I/Q per channel) x (# Channels)/(# Lanes).
This can be rewritten more simply as:
Lane rate = (Interface rate) x (resolution) x (encoding) x (M/L), M = # converters, L = # lanes
In my case this would be:
Lane rate = (375MHz) x (16) x (10/8) x (8/4) = 15Gbps
I have been struggling on this for a little bit and would really like some help. I want to know how an LMFS number of 4-8-3-1-0 is able to support 8 converters at 375 MSPS output rate? Does some amount of data get left out? Or is the assumption that you are only operating for a short amount of time and send the rest of the RX data after you stop sampling?
I expect that I am missing something, but I would really like any help to help me figure out how this works.