AFE7769DEVM: JESD204B Link Not Up

Hi Trong,

Please advise if you are in JESD204B RX (for the AFE), which is the RF transmitter path.

Please advise if your FPGA is sending out K28.5 characters. We would expect the AFE to pull the JESD204B RX SYNC to be logic low to request for K28.5 character, and your FPGA to send out K28.5 character during this time.

Please access the AFE7769D Secure Server to refer to SBAU445 for the JESD204 debug guide. Section 4 mentions various debug strategies in this condition.

-Kang

Hi Kang,

Thank you for your reply. At the moment, I am unable to find the SBAU445 documentation. Could you please provide a reference?

Currently, I am using the JESD204C Xilinx IP Core, configured as shown in the figure. In my previous question, I referred to the EVM; however, I am currently working with the AFE7728D device (not EVM board) and configuring it with an FPGA using the KU11P.        

I checked signal by ILA, the following results were obtained:

Trong

Hi Trong,

For SBAU445, you may download this from the AFE7769D SecureServer

https://www.ti.com/drr/opn/AFE7769D-DESIGN

SBAU445 AFE7769D JESD204 Guide.pdf

Hi Trong

Could you please attach your configuration file for us to review? 

Are you using LVDS SYNC or CMOS SYNC? Do you have flexibility to use CMOS based SYNC?

Marker 1: I believe we should see 0xbcbc characters or K28.5 characters. This is when the SYNC request goes low

Marker 2: is the capture for sync the SYNC signal from the AFE? If so, is this the SYNC_OUT from AFE JESD204 RX for the RF transmitter link, or is it the SYNC_IN from the AFE JESD204 TX for the RF receiver link.

Thank you!

Hello Kang,

Please find my configuration file attached below. I am currently using CMOS SYNC for both the AFE JESD interface and the FPGA.

AFE_JESD204B.txt

In my design, the FPGA uses the Xilinx JESD204C IP core. The rx_sync signal is configured as an output from the Xilinx JESD204 RX IP core and is connected to the AFE JESD. The tx_sync signal is configured as an input to the Xilinx JESD204 TX IP core and is driven by the AFE JESD. 

This is my configuration for JESD204 PHY IP core:

Currently, the JESD204 link between the AFE and the FPGA can be established; however, it is not stable. I have verified the clock configuration and performed a reset of the AFE circuitry, but the issue still persists.

Thank you!

Hi Trong,
Could you please also attach the excel file used to generate the .txt configuration?

I see from the .txt file that AFE side is configured for JESD204B but in your screenshot it shows JESD204C, just want to confirm if this could be the mismatch.

Also can you please share more details on what specific errors do you see when the link is unstable?

Regards,
Bhavesh Atul Rathod.

Hi Bhavesh,
In Vivado 2021.2, only the Xilinx JESD204C IP core is supported. Therefore, the PHY layer is configured as JESD204C with 8B/10B encoding. This configuration is functionally equivalent to the JESD204B operation as described in the documentation.

When the JESD204 link becomes unstable, the AFE JESD204 reports the message:

This is my excel file used to generate the .txt configuration and GPIO AFE pin config:

AFE_JESD204B.xlsx

Thank you!

Trong,
Thank you for the config I will try this on my setup on Monday.

Can you please share more details on what specific errors do you see when the link is unstable? Is just the ADC/DAC side link unstable or both are unstable and what alarms do you see?

You can use below functions to read alarms on AFE serdes receiver side.

Regards,
Bhavesh Atul Rathod.

Hello Bhavesh,

I have used the available alarm indicators to monitor the link status. Based on the results, the AFE JESD204B RX link remains consistently up; however, on the FPGA side, the JESD RX link status is not stable and the “link success” condition is intermittent.

Additionally, during the AFE bring-up process, I frequently encounter the following errors. Could you please help clarify what these errors indicate and what might be causing them?

Thank you very much for your support.

 Trong.

Hi Trong,

Are you working to build a radio or set of radios? If so can you please elaborate on the specific application and design timeline?

Thanks!

BR,

Simran