AFE7950: Problem achieving deterministic latency and clock definition using AFE7950EVM

Rafael Morais

Part Number: AFE7950

Hello,

I am having trouble achieving deterministic latency using AFE7950EVM with ZCU102. I based my design on the reference designs. This was the 8b10b ref design that I updated to use a line rate of 3686.4 MSPS.

I have seen in this post: AFE7950: 4T4R2F 8b10b 2.4576 Gbps SERDES JESD link not always initializing properly where it mentions the need to use an external clock directly to the IP with length matching the sysref signal and without passing through a PLL. The IP datasheet also mentions that for both rx_sys_clock and tx_sys_clock should be sourced independantly.

My problem comes from the fact that tx_sys_clock is limited to "linerate/80" in the case of 64bits data width which is 46.08 MHz. rx_sys_clock says that it can be greater to or equal than linerate/80, and I dont seem to be able to get 46.08 MHz from the lmk on the AFE7950EVM. Is this possible to get or what would be the best way to achieve deterministic latency without changing linerate?

I am only using one TX and one RX channel.

Please guide me through this problem.

24 days ago

0 Roshan N T 3 days ago

TI__Prodigy 40 points

Hi,

Configuring the LMK in PLL mode to achieve 46.08 MHz is not possible because the VCO is running at 2949.12 MHz, and the maximum divider for the LMK clock output is 32.

Instead, the LMK can be configured in divider mode, so the LMK takes an input clock and provides both the FRef and the FPGA reference clock using a divider factor <= 32

Example:

LMK Input Clock: 1474.56 MHz
FRef: 491.52 MHz
FPGA RefClk: 46.08 MHz

Regards,
Roshan

0 Rafael Morais 3 days ago in reply to Roshan N T

Prodigy 65 points

Hi Roshan,

Can you provide the command via script to configure the LMK in divider mode?

Regards,
Rafael Morais

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AFE7950: Problem achieving deterministic latency and clock definition using AFE7950EVM