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Original question:

AFE7950: Expected latency of TI JESD204C IP with AFE7950

AFE7950: Problem achieving deterministic latency and clock definition using AFE7950EVM

Rafael Morais
Prodigy 65 points

Part Number: AFE7950

Hello,

I am having trouble achieving deterministic latency using AFE7950EVM with ZCU102. I based my design on the reference designs. This was the 8b10b ref design that I updated to use a line rate of 3686.4 MSPS.

I have seen in this post: AFE7950: 4T4R2F 8b10b 2.4576 Gbps SERDES JESD link not always initializing properly where it mentions the need to use an external clock directly to the IP with length matching the sysref signal and without passing through a PLL. The IP datasheet also mentions that for both rx_sys_clock and tx_sys_clock should be sourced independantly.

My problem comes from the fact that tx_sys_clock is limited to "linerate/80" in the case of 64bits data width which is 46.08 MHz. rx_sys_clock says that it can be greater to or equal than linerate/80, and I dont seem to be able to get 46.08 MHz from the lmk on the AFE7950EVM. Is this possible to get or what would be the best way to achieve deterministic latency without changing linerate?

I am only using one TX and one RX channel. 

 

Please guide me through this problem.

 

  • 0
    TI__Prodigy 130 points

    Hi,

    Configuring the LMK in PLL mode to achieve 46.08 MHz is not possible because the VCO is running at 2949.12 MHz, and the maximum divider for the LMK clock output is 32.
    Instead, the LMK can be configured in divider mode, so the LMK takes an input clock and provides both the FRef and the FPGA reference clock using a divider factor <= 32
    Example:
    • LMK Input Clock: 1474.56 MHz
    • FRef: 491.52 MHz
    • FPGA RefClk: 46.08 MHz

    Regards,
    Roshan

  • 0 in reply to Roshan N T
    Prodigy 65 points

    Hi Roshan,

    Can you provide the command via script to configure the LMK in divider mode?

    Regards,
    Rafael Morais

  • 0
    TI__Prodigy 130 points

    Hi,

    You would have to set the LMK params section of the bringup script as below.

    ############## LMK Params ##############

    lmkParams.pllEn = False # To configure LMK in divider or distribution mode

    lmkParams.inputClk = 1474.56 # Valid only when lmkParams.pllEn = False

    lmkParams.lmkFrefClk = False # True when AFE Fref is from LMK.

    setupParams.fpgaRefClk = 46.08

    Regards,
    Roshan

  • 0
    TI__Prodigy 130 points

    Hi,

    Please refer the below AFE79xxEVM LMK Clocking Parameters.

    In order to setup the clocking for the AFE79xxEVM LMK the following parameters need to be set:
    • lmkParams.pllEn
       – False: LMK is in distribution/divider mode (Won’t use PLL); True : PLL1 of the LMK will be used with the onboard
    122.88MHz crystal to generate a 2949.12MHz clock from LMK VCO and a 10MHz input through J14 to the LMK can
    be used to frequency lock to equipment.
    • lmkParams.lmkFrefClk
       – False: AFE will not get Fref from LMK; True: AFE will receive the Fref from the LMK.
    • lmkParams.fpgaRefClk
       – Value of the FPGA ref clock from the LMK. This number can be obtained from your lane rate depending on the
    JESD encoding.
       –  For the default firmware: JESD204B: (Lane Rate)/40. JESD204C: (Lane Rate)/66.

    • lmkParams.inputClk
     – This parameter is only valid only when lmkParams.pllEn = False.
     – This is the input through J14 to the LMK. This should be an integer multiple of both your Fref, if the
    AFE will get the Fref from the LMK, and your FPGA ref clock when lmkParams.pllEn = False to use
    the LMK in distribution/divider mode.

    Regards,
    Roshan